在现场可编程门阵列中用于降低泄漏功率的动态电源门控

Hadi JAHANIRAD

doi:10.1631/FITEE.2200084

Your Location：

Home >

Browse articles >

在现场可编程门阵列中用于降低泄漏功率的动态电源门控

常规文章 | Updated：2023-05-08

- 在现场可编程门阵列中用于降低泄漏功率的动态电源门控
  Enhanced Publication
- Dynamic power-gating for leakage power reduction in FPGAs
- 信息与电子工程前沿(英文版) 2023年24卷第4期页码：582-598
- Affiliations：
  
  Department of Electronics and Communication Engineering, University of Kurdistan, Sanandaj 66177-15175, Iran
- Author bio：
  
  Email: h.jahanirad@uok.ac.ir
- Funds：
- DOI：10.1631/FITEE.2200084
  中图分类号： TN79
- 收稿：2022-03-05，
  
  修回：2022-10-10，
  
  纸质出版：2023-04-0
- Accepted：
Scan QR Code
Hadi JAHANIRAD. 在现场可编程门阵列中用于降低泄漏功率的动态电源门控[J]. 信息与电子工程前沿(英文版), 2023,24(4):582-598.

Hadi JAHANIRAD. Dynamic power-gating for leakage power reduction in FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(4): 582-598.
Hadi JAHANIRAD. 在现场可编程门阵列中用于降低泄漏功率的动态电源门控[J]. 信息与电子工程前沿(英文版), 2023,24(4):582-598. DOI： 10.1631/FITEE.2200084.

Hadi JAHANIRAD. Dynamic power-gating for leakage power reduction in FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(4): 582-598. DOI： 10.1631/FITEE.2200084.

摘要

现场可编程门阵列（FPGA）器件由于其低设计成本和可重构性，在电子系统中得到广泛应用。在手持电子系统等电池受限的应用中，低功耗FGPA的需求很大。在现代集成电路技术中，泄漏功率几乎相当于动态功率，因此降低泄漏功率可以显著节省能耗。我们提出一种基于静态随机存取存储器（SRAM）的FPGA高效架构，其中每个模块定义了两种模式（活动模式和休眠模式）。在休眠模式下，模块消耗超低泄漏功率。当模块输出对新输入向量的评估时，模块模式由休眠模式动态改变为活动模式。在产生正确的输出后，该模块返回到休眠模式。所提电路设计在活动模式和休眠模式下都降低了泄漏功耗。通过在FPGA-SPICE软件上实现北卡罗来纳州微电子中心（MCNC）基准电路，将所提出的低泄漏FPGA体系结构与最先进的体系结构进行比较。仿真结果表明，休眠模式下泄漏功耗降低约95%。此外，与以往的最佳设计相比，总功耗（泄漏功耗+动态功耗）降低15%以上。平均面积开销（4.26%）小于其他电源门控设计。

Abstract

Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability. In battery-restricted applications such as handheld electronics systems

low-power FPGAs are in great demand. Leakage power almost equals dynamic power in modern integrated circuit technologies

so the reduction of leakage power leads to significant energy savings. We propose a power-efficient architecture for static random access memory (SRAM) based FPGAs

in which two modes (active mode and sleep mode) are defined for each module. In sleep mode

ultra-low leakage power is consumed by the module. The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors. After producing the correct outputs

the module returns to sleep mode. The proposed circuit design reduces the leakage power consumption in both active and sleep modes. The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina (MCNC) benchmark circuits on FPGA-SPICE software. Simulation results show an approximately 95% reduction in leakage power consumption in sleep mode. Moreover

the total power consumption (leakage+dynamic power consumption) is reduced by more than 15% compared with that of the best previous design. The average area overhead (4.26%) is less than those of other power-gating designs.

关键词

Keywords

references

Ahmed I , Zhao SZ , Trescases O , et al. , 2018 . Automatic application-specific calibration to enable dynamic voltage scaling in FPGAs . IEEE Trans Comput-Aided Des Integr Circ Syst , 37 ( 12 ): 3095 - 3108 . https://doi.org/10.1109/TCAD.2018.2801222 https://doi.org/10.1109/TCAD.2018.2801222

Ahmed I , Shen JL , Betz V , 2020 . Optimizing FPGA logic circuitry for variable voltage supplies . IEEE Trans Very Large Scale Integr Syst , 28 ( 4 ): 890 - 903 . https://doi.org/10.1109/TVLSI.2019.2962501 https://doi.org/10.1109/TVLSI.2019.2962501

Ahmed R , Bsoul AAM , Wilton SJE , et al. , 2014 . High-level synthesis-based design methodology for dynamic power-gated FPGA . Proc 24 th Int Conf on Field Programmable Logic and Applications , p. 1 - 4 . https://doi.org/10.1109/FPL.2014.6927433 https://doi.org/10.1109/FPL.2014.6927433

Ahmed R , Wilton SJE , Hallschmid P , et al. , 2015 . Hierarchical dynamic power-gating in FPGAs . Proc 11 th Int Symp on Applied Reconfigurable Computing , p. 27 - 38 . https://doi.org/10.1007/978-3-319-16214-0_3 https://doi.org/10.1007/978-3-319-16214-0_3

Amara A , Amiel F , Ea T , 2006 . FPGA vs. ASIC for low power applications . Microelectron J , 37 ( 8 ): 669 - 677 . https://doi.org/10.1016/j.mejo.2005.11.003 https://doi.org/10.1016/j.mejo.2005.11.003

Anderson JH , Najm FN , 2006 . Active leakage power optimization for FPGAs . IEEE Trans Comput-Aided Des Integr Circ Syst , 25 ( 3 ): 423 - 437 . https://doi.org/10.1109/TCAD.2005.853692 https://doi.org/10.1109/TCAD.2005.853692

Anderson JH , Najm FN , 2009 . Low-power programmable FPGA routing circuitry . IEEE Trans Very Large Scale Integr Syst , 17 ( 8 ): 1048 - 1060 . https://doi.org/10.1109/TVLSI.2009.2017443 https://doi.org/10.1109/TVLSI.2009.2017443

Bsoul AAM , Wilton SJE , 2010 . An FPGA architecture supporting dynamically controlled power gating . Int Conf on Field-Programmable Technology , p. 1 - 8 . https://doi.org/10.1109/FPT.2010.5681533 https://doi.org/10.1109/FPT.2010.5681533

Bsoul AAM , Wilton SJE , Tsoi KH , et al. , 2016 . An FPGA architecture and CAD flow supporting dynamically controlled power gating . IEEE Trans Very Large Scale Integr Syst , 24 ( 1 ): 178 - 191 . https://doi.org/10.1109/TVLSI.2015.2393914 https://doi.org/10.1109/TVLSI.2015.2393914

Chen DM , Cong J , Dong C , et al. , 2010 . Technology mapping and clustering for FPGA architectures with dual supply voltages . IEEE Trans Comput-Aided Des Integr Circ Syst , 29 ( 11 ): 1709 - 1722 . https://doi.org/10.1109/TCAD.2010.2061770 https://doi.org/10.1109/TCAD.2010.2061770

Chen WT , Li L , Lu P , et al. , 2016 . Design of FPGA's high-speed and low-power programmable interconnect . Proc 13 th IEEE Int Conf on Solid-State and Integrated Circuit Technology , p. 707 - 709 . https://doi.org/10.1109/ICSICT.2016.7999018 https://doi.org/10.1109/ICSICT.2016.7999018

Colleman S , Verhelst M , 2021 . High-utilization, high-flexibility depth-first CNN coprocessor for image pixel processing on FPGA . IEEE Trans Very Large Scale Integr Syst , 29 ( 3 ): 461 - 471 . https://doi.org/10.1109/TVLSI.2020.3046125 https://doi.org/10.1109/TVLSI.2020.3046125

Ebrahimi Z , Khaleghi B , Asadi H , 2017 . PEAF: a power-efficient architecture for SRAM-based FPGAs using reconfigurable hard logic design in dark silicon era . IEEE Trans Comput , 66 ( 6 ): 982 - 995 . https://doi.org/10.1109/TC.2016.2636141 https://doi.org/10.1109/TC.2016.2636141

Hassan H , Anis M , Elmasry M , 2008 . Input vector reordering for leakage power reduction in FPGAs . IEEE Trans Comput-Aided Des Integr Circ Syst , 27 ( 9 ): 1555 - 1564 . https://doi.org/10.1109/TCAD.2008.927673 https://doi.org/10.1109/TCAD.2008.927673

Herath K , Prakash A , Fahmy SA , et al. , 2021 . Power-efficient mapping of large applications on modern heterogeneous FPGAs . IEEE Trans Comput-Aided Des Integr Circ Syst , 40 ( 12 ): 2508 - 2521 . https://doi.org/10.1109/TCAD.2020.3047722 https://doi.org/10.1109/TCAD.2020.3047722

Huda S , Anderson JH , 2017 . Leveraging unused resources for energy optimization of FPGA interconnect . IEEE Trans Very Large Scale Integr Syst , 25 ( 8 ): 2307 - 2320 . https://doi.org/10.1109/TVLSI.2017.2691409 https://doi.org/10.1109/TVLSI.2017.2691409

Ishihara S , Hariyama M , Kameyama M , 2011 . A low-power FPGA based on autonomous fine-grain power gating . IEEE Trans Very Large Scale Integr Syst , 19 ( 8 ): 1394 - 1406 . https://doi.org/10.1109/TVLSI.2010.2050500 https://doi.org/10.1109/TVLSI.2010.2050500

Jahanirad H , 2019 . CC-SPRA: correlation coefficients approach for signal probability-based reliability analysis . IEEE Trans Very Large Scale Integr Syst , 27 ( 4 ): 927 - 939 . https://doi.org/10.1109/TVLSI.2018.2886027 https://doi.org/10.1109/TVLSI.2018.2886027

Kaur I , Rohilla L , Nagpal A , et al. , 2018 . Different configuration of low-power memory design using capacitance scaling on 28-nm field-programmable gate array . In: Muttoo SK (Ed.) , System and Architecture . Springer , Singapore , p. 151 - 161 . https://doi.org/10.1007/978-981-10-8533-8_15 https://doi.org/10.1007/978-981-10-8533-8_15

Khaleghi B , Asadi H , 2018 . A resistive RAM-based FPGA architecture equipped with efficient programming circuitry . IEEE Trans Circ Syst I Regul Pap , 65 ( 7 ): 2196 - 2209 . https://doi.org/10.1109/TCSI.2017.2778113 https://doi.org/10.1109/TCSI.2017.2778113

Kim S , Na S , Kong BY , et al. , 2021 . Real-time SSDLite object detection on FPGA . IEEE Trans Very Large Scale Integr Syst , 29 ( 6 ): 1192 - 1205 . https://doi.org/10.1109/TVLSI.2021.3064639 https://doi.org/10.1109/TVLSI.2021.3064639

Koppa S , John E , 2018 . Performance tradeoffs in the design of low-power SRAM arrays for implantable devices . J Low Power Electron , 14 ( 1 ): 18 - 27 . https://doi.org/10.1166/jolpe.2018.1528 https://doi.org/10.1166/jolpe.2018.1528

Kumar A , Anis M , 2007 . Dual-threshold CAD framework for subthreshold leakage power aware FPGAs . IEEE Trans Comput-Aided Des Integr Circ Syst , 26 ( 1 ): 53 - 66 . https://doi.org/10.1109/TCAD.2006.882595 https://doi.org/10.1109/TCAD.2006.882595

Kuon I , Rose J , 2007 . Measuring the gap between FPGAs and ASICs . IEEE Trans Comput-Aided Des Integr Circ Syst , 26 ( 2 ): 203 - 215 . https://doi.org/10.1109/TCAD.2006.884574 https://doi.org/10.1109/TCAD.2006.884574

Li F , Lin Y , He L , 2004 . Vdd programmability to reduce FPGA interconnect power . IEEE/ACM Int Conf on Computer Aided Design , p. 760 - 765 . https://doi.org/10.1109/ICCAD.2004.1382678 https://doi.org/10.1109/ICCAD.2004.1382678

Li F , Lin Y , He L , 2007 . Field programmability of supply voltages for FPGA power reduction . IEEE Trans Comput-Aided Des Integr Circ Syst , 26 ( 4 ): 752 - 764 . https://doi.org/10.1109/TCAD.2006.884848 https://doi.org/10.1109/TCAD.2006.884848

Li J , Chow P , Peng YX , et al. , 2021 . FPGA implementation of an improved OMP for compressive sensing reconstruction . IEEE Trans Very Large Scale Integr Syst , 29 ( 2 ):‍ 259 - 272 . https://doi.org/10.1109/TVLSI.2020.3030906 https://doi.org/10.1109/TVLSI.2020.3030906

Lin MJ , El Gamal A , 2009 . A low-power field-programmable gate array routing fabric . IEEE Trans Very Large Scale Integr Syst , 17 ( 10 ): 1481 - 1494 . https://doi.org/10.1109/TVLSI.2008.2005098 https://doi.org/10.1109/TVLSI.2008.2005098

Lin Y , He L , 2006 . Dual-Vdd interconnect with chip-level time slack allocation for FPGA power reduction . IEEE Trans Comput-Aided Des Integr Circ Syst , 25 ( 10 ):‍ 2023 - 2034 . https://doi.org/10.1109/TCAD.2006.870858 https://doi.org/10.1109/TCAD.2006.870858

Luu J , Goeders J , Wainberg M , et al. , 2014 . VTR 7.0: next generation architecture and CAD system for FPGAs . ACM Trans Reconfig Technol Syst , 7 ( 2 ): 6 . https://doi.org/10.1145/2617593 https://doi.org/10.1145/2617593

Ma YF , Cao Y , Vrudhula S , et al. , 2018 . Optimizing the convolution operation to accelerate deep neural networks on FPGA . IEEE Trans Very Large Scale Integr Syst , 26 ( 7 ): 1354 - 1367 . https://doi.org/10.1109/TVLSI.2018.2815603 https://doi.org/10.1109/TVLSI.2018.2815603

Mitra J , Nayak TK , 2018 . An FPGA-based phase measurement system . IEEE Trans Very Large Scale Integr Syst , 26 ( 1 ): 133 - 142 . https://doi.org/10.1109/TVLSI.2017.2758807 https://doi.org/10.1109/TVLSI.2017.2758807

Nguyen DT , Nguyen TN , Kim H , et al. , 2019 . A high-throughput and power-efficient FPGA implementation of YOLO CNN for object detection . IEEE Trans Very Large Scale Integr Syst , 27 ( 8 ): 1861 - 1873 . https://doi.org/10.1109/TVLSI.2019.2905242 https://doi.org/10.1109/TVLSI.2019.2905242

Nunez-Yanez JL , Hosseinabady M , Beldachi A , 2016 . Energy optimization in commercial FPGAs with voltage, frequency and logic scaling . IEEE Trans Comput , 65 ( 5 ):‍ ‍1484 - 1493 . https://doi.org/10.1109/TC.2015.2435771 https://doi.org/10.1109/TC.2015.24357

Qi H , Ayorinde O , Calhoun BH , 2017 . An ultra-low-power FPGA for IoT applications . IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf , p. 1 - 3 . https://doi.org/10.1109/S3S.2017.8308753 https://doi.org/10.1109/S3S.2017.8308753

Rahimi H , Jahanirad H , 2021 . An evolutionary approach to implement logic circuits on three dimensional FPGAs . Expert Syst Appl , 174 : 114780 . https://doi.org/10.1016/j.eswa.2021.114780 https://doi.org/10.1016/j.eswa.2021.114780

Ramesh NVK , Uday Kiran K , Reshma NKSVS , et al. , 2021 . An efficient way to optimize the FPGA routing architecture . Proc 6 th Int Conf on Communication and Electronics Systems , p. 209 - 211 . https://doi.org/10.1109/ICCES51350.2021.9489142 https://doi.org/10.1109/ICCES51350.2021.9489142

Ravishankar C , Anderson JH , Kennings A , 2012 . FPGA power reduction by guarded evaluation considering logic architecture . IEEE Trans Comput-Aided Des Integr Circ Syst , 31 ( 9 ): 1305 - 1318 . https://doi.org/10.1109/TCAD.2012.2192478 https://doi.org/10.1109/TCAD.2012.2192478

Savari MA , Jahanirad H , 2020 . NN-SSTA: a deep neural network approach for statistical static timing analysis . Expert Syst Appl , 149 : 113309 . https://doi.org/10.1016/j.eswa.2020.113309 https://doi.org/10.1016/j.eswa.2020.113309

Seifoori Z , Khaleghi B , Asadi H , 2017 . A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era . Design, Automation & Test in Europe Conf & Exhibition , p. 1342 - 1347 . https://doi.org/10.23919/DATE.2017.7927201 https://doi.org/10.23919/DATE.2017.7927201

Seifoori Z , Asadi H , Stojilović M , 2019 . A machine learning approach for power gating the FPGA routing network . Int Conf on Field-Programmable Technology , p. 10 - 18 . https://doi.org/10.1109/ICFPT47387.2019.00010 https://doi.org/10.1109/ICFPT47387.2019.00010

Seifoori Z , Asadi H , Stojilović M , 2021 . Shrinking FPGA static power via machine learning-based power gating and enhanced routing . IEEE Access , 9 : 115599 - 115619 . https://doi.org/10.1109/ACCESS.2021.3085005 https://doi.org/10.1109/ACCESS.2021.3085005

Seomun J , Shin Y , 2011 . Design and optimization of power-gated circuits with autonomous data retention . IEEE Trans Very Large Scale Integr Syst , 19 ( 2 ): 227 - 236 . https://doi.org/10.1109/TVLSI.2009.2033356 https://doi.org/10.1109/TVLSI.2009.2033356

Singh P , Reniwal BS , Vijayvargiya V , et al. , 2018 . Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design . Integration , 62 : 1 - 13 . https://doi.org/10.1016/j.vlsi.2018.03.006 https://doi.org/10.1016/j.vlsi.2018.03.006

Tan BL , Lee WK , Mok KM , et al. , 2018 . Clock gating implementation on commercial field programmable gate array (FPGA) . Proc 4 th Int Conf on Electrical, Electronics and System Engineering , p. 102 - 106 . https://doi.org/10.1109/ICEESE.2018.8703530 https://doi.org/10.1109/ICEESE.2018.8703530

Tang XF , Giacomin E , De Micheli G , et al. , 2018 . Post-P&R performance and power analysis for RRAM-based FPGAs . IEEE J Emerg Sel Top Circ Syst , 8 ( 3 ): 639 - 650 . https://doi.org/10.1109/JETCAS.2018.2847600 https://doi.org/10.1109/JETCAS.2018.2847600

Tang XF , Giacomin E , De Micheli G , et al. , 2019 . FPGA-SPICE: a simulation-based architecture evaluation framework for FPGAs . IEEE Trans Very Large Scale Integr Syst , 27 ( 3 ): 637 - 650 . https://doi.org/10.1109/TVLSI.2018.2883923 https://doi.org/10.1109/TVLSI.2018.2883923

Tatsumura K , Yazdanshenas S , Betz V , 2018 . Enhancing FPGAs with magnetic tunnel junction‍-based block RAMs . ACM Trans Reconfig Technol Syst , 11 ( 1 ): 6 . https://doi.org/10.1145/3154425 https://doi.org/10.1145/3154425

Tuan T , Rahman A , Das S , et al. , 2007 . A 90-nm low-power FPGA for battery-powered applications . IEEE Trans Comput-Aided Des Integr Circ Syst , 26 ( 2 ): 296 - 300 . https://doi.org/10.1109/TCAD.2006.885731 https://doi.org/10.1109/TCAD.2006.885731

Vo MH , 2018 . The merged clock gating architecture for low power digital clock application on FPGA . Int Conf on Advanced Technologies for Communications , p. 282 - 286 . https://doi.org/10.1109/ATC.2018.8587596 https://doi.org/10.1109/ATC.2018.8587596

Wagle A , Vrudhula S , 2022 . Heterogeneous FPGA architecture using threshold logic gates for improved area, power, and performance . IEEE Trans Comput-Aided Des Integr Circ Syst , 41 ( 6 ): 1855 - 1867 . https://doi.org/10.1109/TCAD.2021.3099780 https://doi.org/10.1109/TCAD.2021.3099780

Zhu JF , Pan LY , Yan YR , et al. , 2014 . A fast application-based supply voltage optimization method for dual voltage FPGA . IEEE Trans Very Large Scale Integr Syst , 22 ( 12 ):‍ 2629 - 2634 . https://doi.org/10.1109/TVLSI.2013.2296791 https://doi.org/10.1109/TVLSI.2013.2296791

浏览量

724

Downloads

CSCD

文章被引用时，请邮件提醒。

Submit

工具集

关联资源

A floating point conversion algorithm for mixed precision computations