Design and analysis of carbon nanotube FET based quaternary full adders

Mohammad Hossein MOAIYERI; Shima SEDIGHIANI; Fazel SHARIFI; Keivan NAVI

doi:10.1631/FITEE.1500214

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Design and analysis of carbon nanotube FET based quaternary full adders

Regular Papers | Updated：2022-05-19

- Design and analysis of carbon nanotube FET based quaternary full adders
- 碳纳米管场效应管四进制全加器设计与分析
- Frontiers of Information Technology & Electronic Engineering Vol. 17, Issue 10, Pages: 1056-1066(2016)
- Affiliations：
  
  1Faculty of Electrical Engineering, Shahid Beheshti University, Tehran 1983963113, Iran
  2Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, Tehran 1983963113, Iran
- Author bio：
  
  E-mail: h_moaiyeri@sbu.ac.ir
- Funds：
- DOI：10.1631/FITEE.1500214
  CLC： TN79
- Received：07 July 2015，
  
  Accepted：24 September 2016，
  
  Published：2016-10
- Accepted：
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Mohammad Hossein MOAIYERI, Shima SEDIGHIANI, Fazel SHARIFI, et al. Design and analysis of carbon nanotube FET based quaternary full adders[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(10): 1056-1066.
DOI：

Mohammad Hossein MOAIYERI, Shima SEDIGHIANI, Fazel SHARIFI, et al. Design and analysis of carbon nanotube FET based quaternary full adders[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(10): 1056-1066. DOI： 10.1631/FITEE.1500214.

摘要

CMOS二进制逻辑受短沟道效应、功率密度及互连约束等条件的限制。非硅多值逻辑计算是克服上述问题的一种有效方案。本研究在碳纳米管场效应管（carbon nanotube field effect transistors

CNTFET）的基础上提出了两种高性能四进制全加单元。该全加单元利用了CNTFET独有的特性，如目标电压阈值可通过调整碳纳米管管径控制、CNTFET具有与p型和n型器件相同的迁移性。通过在Synopsys HSPICE中使用32 nm斯坦福综合CNTFET模型，在多种测试条件下对所述电路单元进行了仿真。与当前水平的四进制全加器相比，本文所采用的设计平均降低延迟32%，所需平均功率、能耗及静态功率分别为现有水平的68%、83%及77%。仿真结果表明，所述设计在生产制程、电压、温度变化、噪声耐受方面具有较好的鲁棒性。

Abstract

CMOS binary logic is limited by short channel effects

power density

and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay

68% average power

83% energy consumption

and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process

voltage

and temperature variations

and are noise tolerant.

关键词

Keywords

references

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