Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

Liang GENG; Ji-zhong SHEN; Cong-yuan XU

doi:10.1631/FITEE.1500293

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Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

Regular Papers | Updated：2022-05-19

- Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
- 采用内嵌时钟控制技术的低功耗双边沿隐形脉冲触发器
- Frontiers of Information Technology & Electronic Engineering Vol. 17, Issue 9, Pages: 962-972(2016)
- Affiliations：
  
  College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China
- Author bio：
  
  E-mail:gengliang@zju.edu.cn
  E-mail:jzshen@zju.edu.cn
  E-mail:cyxu@zju.edu.cn
- Funds：
- DOI：10.1631/FITEE.1500293
  CLC： TN432
- Received：08 September 2015，
  
  Accepted：17 February 2016，
  
  Published：2016-09
- Accepted：
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Liang GENG, Ji-zhong SHEN, Cong-yuan XU. Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 962-972.
DOI：

Liang GENG, Ji-zhong SHEN, Cong-yuan XU. Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 962-972. DOI： 10.1631/FITEE.1500293.

摘要

本文提出了一种新颖的采用内嵌时钟控制技术的双边沿隐形脉冲触发器（dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

DIFF-CGS），其在脉冲产生模块中采用了基于时钟控制技术的传输门逻辑。该技术在输入信号不变时关闭反相器链，抑制延迟的时钟信号和锁存器中的冗余跳变，从而降低触发器的功耗。基于SMIC 65 nm工艺的后端仿真结果显示，与相关文献中的同类脉冲型触发器相比，在输入信号开关转换率为10%时，本文提出的DIFF-CGS减少了41.39%–56.21%的功耗。此外，在隐形脉冲发生模块和静态锁存器中节点的全摆幅跳变特性提高了电路的鲁棒性。所以，DIFF-CGS适用于信号转换频率较低的低功耗超大规模集成电路（very-large-scale integration

VLSI）中。

Abstract

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed

which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged

so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated

leading to low power efficiency. Based on SMIC 65 nm technology

extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption

compared with its counterparts at 10% data-switching activity. Also

full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus

DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

关键词

Keywords

references

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