A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm

Xing-ru PENG; Wei ZHANG; Yan-yan LIU

doi:10.1631/FITEE.1500303

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A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm

Regular Papers | Updated：2022-05-19

- A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm
- 一款基于改进的步进式译码算法的流水线架构RS码译码器
- Frontiers of Information Technology & Electronic Engineering Vol. 17, Issue 9, Pages: 954-961(2016)
- Affiliations：
  
  1.School of Electronic and Information Engineering, Tianjin University, Tianjin 300072, China
  2.College of Electronic Information and Optical Engineering, Nankai University, Tianjin 300071, China
- Author bio：
  
  E-mail:tjupengxr@tju.edu.cn
  E-mail:tjuzhangwei@tju.edu.cn
  E-mail:lyytianjin@nankai.edu.cn
- Funds：
- DOI：10.1631/FITEE.1500303
  CLC： TN432
- Received：20 September 2015，
  
  Accepted：16 February 2016，
  
  Published：2016-09
- Accepted：
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Xing-ru PENG, Wei ZHANG, Yan-yan LIU. A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 954-961.
DOI：

Xing-ru PENG, Wei ZHANG, Yan-yan LIU. A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 954-961. DOI： 10.1631/FITEE.1500303.

摘要

基于改进的步进式译码算法，我们为超宽带系统设计了一款流水线架构的Reed-Solomon(RS)码译码器。为了减小复杂度，改进的步进式译码算法将传统步进式译码算法中冗余的两部分进行了结合。此外，采用流水线架构，使得所设计的译码器以最小时延获得最大吞吐率。因此，对于RS（23

17）码，我们所设计的译码器面积比ME（modified Euclidean）架构和pDCME（pipelined degree-computationless modified Euclidean）架构分别减少了42.5%和24.4%。此外，与传统步进式译码器相比，我们设计的译码器能减少11.3%的面积，且关键路径延迟更低。

Abstract

We propose a pipelined Reed-Solomon (RS) decoder for an ultra-wideband system using a modified stepby-step algorithm. To reduce the complexity

the modified step-by-step algorithm merges two cases of the original algorithm. The pipelined structure allows the decoder to work at high rates with minimum delay. Consequently

for RS(23

17) codes

the proposed architecture requires 42.5% and 24.4% less area compared with a modified Euclidean architecture and a pipelined degree-computationless modified Euclidean architecture

respectively. The area of the proposed decoder is 11.3% less than that of the previous step-by-step decoder with a lower critical path delay.

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references

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