Wide-range tracking technique for process-variation-robust clock and data recovery applications

Jun-sheng LV; You LI; Yu-mei ZHOU; Jian-zhong ZHAO; Hai-hua SHEN; Feng ZHANG

doi:10.1631/FITEE.1500410

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Wide-range tracking technique for process-variation-robust clock and data recovery applications

Regular Papers | Updated：2022-05-19

- Wide-range tracking technique for process-variation-robust clock and data recovery applications
- 一种针对工艺变化鲁棒性时钟数据恢复应用的宽范围追踪技术
- Frontiers of Information Technology & Electronic Engineering Vol. 18, Issue 5, Pages: 729-737(2017)
- Affiliations：
  
  1Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  2University of Chinese Academy of Sciences, Beijing 100029, China
- Author bio：
  
  E-mail:lvjunsheng@ime.ac.cn
  E-mail:shenhh@ucas.ac.cn
  E-mail:zhangfeng_ime@ime.ac.cn
- Funds：
- DOI：10.1631/FITEE.1500410
  CLC： TN432
- Received：15 November 2015，
  
  Accepted：02 March 2016，
  
  Published：2017-05
- Accepted：
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Jun-sheng LV, You LI, Yu-mei ZHOU, et al. Wide-range tracking technique for process-variation-robust clock and data recovery applications[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(5): 729-737.
DOI：

Jun-sheng LV, You LI, Yu-mei ZHOU, et al. Wide-range tracking technique for process-variation-robust clock and data recovery applications[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(5): 729-737. DOI： 10.1631/FITEE.1500410.

摘要

本文提出了一种针对时钟数据恢复电路的宽范围追踪技术。与传统技术相比，本文采用带校准的数字时钟数据恢复控制器，拓展了追踪范围；同时，时钟数据恢复电路对工艺和电源电压的变化不再敏感。为了验证该技术，整个时钟数据恢复电路采用65 nm CMOS工艺实现。测试结果表明在5 Gb/s数据率下，追踪范围大于±6×10

−3

。整体接收器拥有良好的抖动容限，且误码率达到了

−2

。重新采样和串化后的串行数据的均方根抖动仅为6.7 ps。

Abstract

A wide-range tracking technique for clock and data recovery (CDR) circuit is presented. Compared to the traditional technique

a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design

CDR is not sensitive to process and power supply variations. To verify the technique

the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±610

−3

at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of

–12

. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.

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Keywords

references

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