Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs

Ying-hui ZHONG; Shu-xiang SUN; Wen-bin WONG; Hai-li WANG; Xiao-ming LIU; Zhi-yong DUAN; Peng DING; Zhi JIN

doi:10.1631/FITEE.1601121

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Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs

Regular Papers | Updated：2022-05-19

- Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs
- 结合选择性和数字湿法腐蚀的InAlAs/InGaAs InP基HEMTs两步栅槽腐蚀工艺
- Frontiers of Information Technology & Electronic Engineering Vol. 18, Issue 8, Pages: 1180-1185(2017)
- Affiliations：
  
  School of Physics and Engineering, Zhengzhou University, Zhengzhou 450001, China
  Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
- Author bio：
  
  [ "Ying-hui ZHONG, E-mail: zhongyinghui@zzu.edu.cn" ]
  Zhi JIN, E-mail: jinzhi@ime.ac.cn
- Funds：
- DOI：10.1631/FITEE.1601121
  CLC： TN385
- Received：25 February 2016，
  
  Revised：2017-;8-;6，
  
  Published：2017-08
- Accepted：
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Ying-hui ZHONG, Shu-xiang SUN, Wen-bin WONG, et al. Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(8): 1180-1185.
DOI：

Ying-hui ZHONG, Shu-xiang SUN, Wen-bin WONG, et al. Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(8): 1180-1185. DOI： 10.1631/FITEE.1601121.

摘要

本文针对InAlAs/InGaAs InP基高电子迁移率晶体管（High electron mobility transistors

HEMTs）提出了一种结合高选择性湿法腐蚀和非选择性数字湿法腐蚀的两步栅槽腐蚀工艺。通过采用丁二酸和双氧水（H

）混合溶液，InGaAs与InAlAs材料的腐蚀选择比可以超过100。该选择性湿法腐蚀工艺在InAlAs/InGaAs InP基HEMTs栅槽工艺中得到了很好的验证，栅槽腐蚀会自动终止在InAlAs势垒层。本文通过分离氧化/去氧化过程开发了非选择性数字湿法腐蚀工艺，每个周期能除去1.2 nm InAlAs材料。最终，两步栅槽腐蚀工艺被成功用于器件制备中，数字湿法腐蚀重复两个周期去掉约3 nm InAlAs势垒层材料。通过该方法制备的InP基HEMTs器件比只依靠选择性湿法腐蚀栅槽工艺制备出的器件具有更短的栅沟间距，表现出更好的有效跨导和射频特性。

Abstract

A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors (HEMTs). High etching-selectivity ratio of InGaAs to InAlAs material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide (H

). Selective wet-etching is validated in the gate-recess process of InAlAs/InGaAs InP-based HEMTs

which proceeds and automatically stops at the InAlAs barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique

and during each digital etching cycle 1.2 nm InAlAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAlAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic transconductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.

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references

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