A highly efficient reconfigurable rotation unit based on an inverse butterfly network

Chao MA; Zi-bin DAI; Wei LI; Hai-juan ZANG

doi:10.1631/FITEE.1601265

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A highly efficient reconfigurable rotation unit based on an inverse butterfly network

Regular Papers | Updated：2022-05-19

- A highly efficient reconfigurable rotation unit based on an inverse butterfly network
- 基于Inverse Butterlfy网络的高效可重构循环移位单元
- Frontiers of Information Technology & Electronic Engineering Vol. 18, Issue 11, Pages: 1784-1794(2017)
- Affiliations：
  
  Department of Electrical Engineering, Zhengzhou Institute of Information Science and Technology, Zhengzhou 450004, China
  State Key Lab of ASIC and System, Fudan University, Shanghai 200240, China
  School of Computer Engineering, Jiangsu University of Technology, Changzhou 213001, China
- Author bio：
  
  [ "Chao MA, E-mail: wenlu_ma@163.com" ]
  Zi-bin DAI, E-mail:Daizb2004@126.com
- Funds：
- DOI：10.1631/FITEE.1601265
  CLC： TP331.2
- Published：2017-11，
  
  Received：17 May 2016，
  
  Revised：20 November 2017，
- Accepted：
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CHAO MA, ZI-BIN DAI, WEI LI, et al. A highly efficient reconfigurable rotation unit based on an inverse butterfly network. [J]. Frontiers of information technology & electronic engineering, 2017, 18(11): 1784-1794.
DOI：

CHAO MA, ZI-BIN DAI, WEI LI, et al. A highly efficient reconfigurable rotation unit based on an inverse butterfly network. [J]. Frontiers of information technology & electronic engineering, 2017, 18(11): 1784-1794. DOI： 10.1631/FITEE.1601265.

摘要

本文提出了一种利用inverse butterfly网络的自路由特性完成循环移位、短字循环移位等操作的可重构控制信息生成算法。该算法具有高并行度和低成本，此外还支持循环移位、双向循环移位以及短字循环移位操作。据我们所知，这是首个将多种不同类型的循环移位操作统一在一个硬件架构中的算法。本文进一步设计了一种高效可重构循环移位单元，并在SMIC 65-nm工艺下实现了逻辑综合。结果表明：与以往具有相似功能的设计相比，该单元的效能至少提升了23%；当仅支持双向循环移位操作时，该单元具有更小的面积和更低的延迟。

Abstract

We propose a reconfigurable control-bit generation algorithm for rotation and sub-word rotation operations. The algorithm uses a self-routing characteristic to configure an inverse butterfly network. In addition to being highly parallelized and inexpensive

the algorithm integrates the rotation-shift

bi-directional rotation-shift

and sub-word rotation-shift operations. To our best knowledge

this is the first scheme to accommodate a variety of rotation operations into the same architecture. We have developed the highly efficient reconfigurable rotation unit (HERRU) and synthesized it into the Semiconductor Manufacturing International Corporation (SMIC)'s 65-nm process. The results show that the overall efficiency (relative area×relative latency) of our HERRU is higher by at least 23% than that of other designs with similar functions. When executing the bi-directional rotation operations alone

HERRU occupies a significantly smaller area with a lower latency than previously proposed designs.

关键词

循环移位操作自路由控制信息生成算法Inverse butterfly网络

Keywords

Rotation operationsSelf-routingControl-bit generation algorithmInverse butterfly network

references

G. Bansod, , , N. Raval, , , N. Pisharoty. . Implementation of a new lightweight encryption design for embedded security. . IEEE Trans. Inform. Forens. Secur., , 2014. . 10((1):):142--151. . DOI:10.1109/TIFS.2014.2365734http://doi.org/10.1109/TIFS.2014.2365734..

A. Belazi, , , A. El-Latif, , , S. Belghith. . A novel image encryption scheme based on substitution-permutation network and chaos, , Signal Process., , 2016. . 128155--170. . DOI:10.1016/j.sigpro.2016.03.021http://doi.org/10.1016/j.sigpro.2016.03.021..

Z. Chang, , , J. Hu, , , C. Zheng, , , 等. . Research on shifter based on iButterfly network. . Commun. Comput. Inform. Sci., , 2013. . 39692--100. . DOI:10.1007/978-3-642-41635-4_10http://doi.org/10.1007/978-3-642-41635-4_10..

H. Dai, , , X. Shen. . Rearrageability of the 7-stage 16×16 shuffle exchange network. . Acta Electron. Sin., , 2007. . 35((10):):1875--1891. . ..

Y. Hilewitz, , , R.B. Lee. . Fast bit compression and expansion with parallel extract and parallel deposit instructions. . IEEE Int. Conf. on Application-Specific Systems, , 2006. . p.65--72. . DOI:10.1109/ASAP.2006.33http://doi.org/10.1109/ASAP.2006.33..

Y. Hilewitz, , , R.B. Lee. . Performing advanced bit manipulations efficiently in general-purpose processors. . IEEE Symp. on Computer Arithmetic, , 2007. . p.251--260. . DOI:10.1109/ARITH.2007.27http://doi.org/10.1109/ARITH.2007.27..

Y. Hilewitz, , , R.B. Lee. . Fast bit gather, bit scatter and bit permutation instructions for commodity microprocessors. . J. Signal Process. Syst., , 2008. . 53((2):):145--169. . DOI:10.1007/s11265-008-0212-8http://doi.org/10.1007/s11265-008-0212-8..

Y. Hilewitz, , , R.B. Lee. . A new basis for shifters in general-purpose processors for existing and advanced bit manipulations. . IEEE Trans. Comput., , 2009. . 58((8):):1035--1048. . DOI:10.1109/TC.2008.219http://doi.org/10.1109/TC.2008.219..

Y. Hilewitz, , , Z.J. Shi, , , R.B. Lee. . Comparing fast implementations of bit permutation instructions. . Proc. 38th Annual Asilomar Conf. on Signals, Systems, and Computers, , 2004. . p.1856--1863. . DOI:10.1109/ACSSC.2004.13994865http://doi.org/10.1109/ACSSC.2004.13994865..

Intel Corporation. . Intel Itanium Architecture Software Developer's Manual. . https://www.intel.com/content/www/us/en/processors/itanium/itanium-architecture-vol-3-manual.htmlhttps://www.intel.com/content/www/us/en/processors/itanium/itanium-architecture-vol-3-manual.html [Accessedon April 5, 2016], , 2006. . Vol. 3Rev. 2.2..

Intel Corporation. . Intel® 64 and IA-32 Architectures Software Developer's Manual. . https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdfhttps://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf [Accessed on April 10, 2016], , 2015. ..

A. Jolfaei, , , X. Wu, , , V. Muthukkumarasamy. . On the security of permutation-only image encryption schemes. . IEEE Trans. Inform. Forens. Secur., , 2015. . 11((2):):235--246. . DOI:10.1109/TIFS.2015.2489178http://doi.org/10.1109/TIFS.2015.2489178..

R.B. Lee, , , Z.J. Shi, , , Y.L. Yin, , , 等. . On permutation operations in cipher design. . Int. Conf. on Information Technology: Coding and Computing, , 2004. . p.569--577. . DOI:10.1109/ITCC.2004.1286714http://doi.org/10.1109/ITCC.2004.1286714..

D. Nassimi, , , S. Sahni. . A self-routing benes network and parallel permutation algorithm. . IEEE Trans. Comput., , 1981. . 30((8):):332--340. . DOI:10.1109/TC.1981.1675791http://doi.org/10.1109/TC.1981.1675791..

M.R. Pillmeier. . Pillmeier, M.R., 2002. Barrel Shifter Design, Optimization, and Analysis. . MS Thesis, Lehigh University, Bethlehem, Pennsylvania, , 2002. ..

M.R. Pillmeier, , , M.J. Schulte, , , E.G.Ⅲ Walters. . Design alternatives for barrel shifters. . Proc. Advanced Signal Processing Algorithms, Architectures, and Implementations, , 2002. . p.436--447. . DOI:10.1117/12.452034http://doi.org/10.1117/12.452034..

S. Rajkumar, , , N.K. Goyal. . Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection networks. . J. Supercomput., , 2014. . 69((1):):468--491. . DOI:10.1007/s11227-014-1175-0http://doi.org/10.1007/s11227-014-1175-0..

P.V. Saraswathi, , , M. Venkatesulu. . A block cipher based on Boolean matrices using bit level operations. . IEEE/ ACIS 13th Int. Conf. on Computer and Information Science, , 2014. . p.59--63. . DOI:10.1109/ICIS.2014.6912108http://doi.org/10.1109/ICIS.2014.6912108..

G. Sayilar, , , D. Chiou. . Cryptoraptor: high-throughput reconfigurable cryptographic processor. . IEEE/ACM Int. Conf. on Computer-Aided Design, , 2015. . p.155--161. . DOI:10.1109/ICCAD.2014.7001346http://doi.org/10.1109/ICCAD.2014.7001346..

Semiconductor Manufacturing International Corporation. . SMIC 55nm Low Leakage Logic Process Standard Cell Library Databook v2.0. . 2012. ..

Z.J. Shi, , , X. Yang, , , R.B. Lee. . Alternative applicationspecific processor architectures for fast arbitrary bit permutations. . Int. J. Embed. Syst., , 2008. . 3((4):):219--228. . DOI:10.1504/IJES.2008.022393http://doi.org/10.1504/IJES.2008.022393..

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