A multistandard and resource-efficient Viterbi decoder for a multimode communication system

Yi-qi XIE; Zhi-guo YU; Yang FENG; Lin-na ZHAO; Xiao-feng GU

doi:10.1631/FITEE.1601596

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A multistandard and resource-efficient Viterbi decoder for a multimode communication system

Regular Papers | Updated：2022-05-19

- A multistandard and resource-efficient Viterbi decoder for a multimode communication system
- 一种面向多模通讯系统的多标准低资源消耗Viterbi译码器
- Frontiers of Information Technology & Electronic Engineering Vol. 19, Issue 4, Pages: 536-543(2018)
- Affiliations：
  
  MOE Engineering Research Center of IoT Technology Applications, Wuxi 214122, China
  Department of Electronic Engineering, Jiangnan University, Wuxi 214122, China
- Author bio：
  
  Zhi-guo YU, E-mail: yuzhiguo@jiangnan.edu.cn
- Funds：
- DOI：10.1631/FITEE.1601596
  CLC： TN764
- Received：02 October 2016，
  
  Revised：2018-;4-12，
  
  Published：2018-04
- Accepted：
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Yi-qi XIE, Zhi-guo YU, Yang FENG, et al. A multistandard and resource-efficient Viterbi decoder for a multimode communication system[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(4): 536-543.
DOI：

Yi-qi XIE, Zhi-guo YU, Yang FENG, et al. A multistandard and resource-efficient Viterbi decoder for a multimode communication system[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(4): 536-543. DOI： 10.1631/FITEE.1601596.

摘要

基于一种新型标准卷积码码字生成单元设计一种多参数可重构Viterbi译码器，优化译码器的资源消耗，提高对多参数的兼容性。标准卷积码码字生成单元用于产生所有状态码，采用迭代运算方式计算所有可能存在的标准卷积码码字。在重新计算分支度量值及对度量值与转换路径重新排序时，基于新型准卷积码码字生成单元的Viterbi译码器结构能够减少运算资源消耗。多参数可重构Viterbi译码器结构能够支持范围为3–9的可变约束长度，1/2、1/3、1/4的可变码率，以及完全可配置的约束多项式。该Viterbi译码器采用Xilinx XC7VX485T FPGA平台实现，具有高达200 Mbps的吞吐率，使用逻辑门的数量为162 k，具有较低的资源消耗。

Abstract

We present a novel standard convolutional symbols generator (SCSG) block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters. The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach. The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths. The proposed architecture supports constraint lengths from 3 to 9

code rates of 1/2

1/3

and 1/4

and fully optional polynomials. The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.

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references

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