Real-time pre-processing system with hardware accelerator for mobile core networks<sup>#</sup>

Mian CHENG; Jin-shu SU; Jing XU

doi:10.1631/FITEE.1700507

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Real-time pre-processing system with hardware accelerator for mobile core networks^#

Regular Papers | Updated：2022-05-19

- Real-time pre-processing system with hardware accelerator for mobile core networks^#
- 基于硬件加速的移动核心网实时预处理系统
- Frontiers of Information Technology & Electronic Engineering Vol. 18, Issue 11, Pages: 1720-1731(2017)
- Affiliations：
  
  College of Computer, National University of Defense Technology, Changsha 410073, China
- Author bio：
  
  [ "Mian CHENG, E-mail: cm@nudt.edu.cn" ]
  Jin-shu SU, E-mail: sjs@nudt.edu.cn
  [ "Jing XU, E-mail: jing.xu@nudt.edu.cn" ]
- Funds：
- DOI：10.1631/FITEE.1700507
  CLC： TP309.2
- Received：02 August 2017，
  
  Revised：2017-11-23，
  
  Published：2017-11
- Accepted：
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Mian CHENG, Jin-shu SU, Jing XU. Real-time pre-processing system with hardware accelerator for mobile core networks^#[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(11): 1720-1731.
DOI：

Mian CHENG, Jin-shu SU, Jing XU. Real-time pre-processing system with hardware accelerator for mobile core networks^#[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(11): 1720-1731. DOI： 10.1631/FITEE.1700507.

摘要

随着用作通信终端或平台的移动设备越来越多，电信基础设施安全受到的威胁日益严重。作为一种移动核心网关的旁路设备，网络探测工具可以收集和分析所有经过网关的数据流量，并进行安全检测。但随着核心网链路带宽的不断提高，如何有效降低安全检测系统的处理压力是一项重要挑战。在本文中，我们设计并评估了一个由硬件加速器和多核处理器构成的报文实时预处理系统，能够快速恢复移动核心网链路中每个封装和压缩的数据包，并有效地将还原后的流量分配到多个后端安全检测系统。使用大量真实数据对系统进行测试，结果表明，我们的预处理系统可以处理所有类型的通信协议报文，并实现至少18 Gb/s的处理速率。

Abstract

With the rapidly increasing number of mobile devices being used as essential terminals or platforms for communication

security threats now target the whole telecommunication infrastructure and become increasingly serious. Network probing tools

which are deployed as a bypass device at a mobile core network gateway

can collect and analyze all the traffic for security detection. However

due to the ever-increasing link speed

it is of vital importance to offload the processing pressure of the detection system. In this paper

we design and evaluate a real-time pre-processing system

which includes a hardware accelerator and a multi-core processor. The implemented prototype can quickly restore each encapsulated packet and effectively distribute traffic to multiple back-end detection systems. We demonstrate the prototype in a well-deployed network environment with large volumes of real data. Experimental results show that our system can achieve at least 18 Gb/s with no packet loss with all kinds of communication protocols.

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Keywords

references

L. Cavigelli , , , D. Gschwend , , , C. Mayer , , , 等 . . Origami: a convolutional network accelerator . . Proc. 25th Edition on Great Lakes Symp. on VLSI , , 2015 . . p.199 - - 204 . . DOI: 10.1145/2742060.2743766 http://doi.org/10.1145/2742060.2743766 . .

M. Cheng , , , Y. Sun , , , J. Su . . A real-time pre-processing system for mobile core network measurement . . Proc. 6th Int. Conf. on Instrumentation, Measurement, Computer, Communication adn Control , , 2016 . . p.298 - - 302 . . DOI: 10.1109/IMCCC.2016.73 http://doi.org/10.1109/IMCCC.2016.73 . .

Communications Standards Association China , , , c. In . . Inc. . . Third Generation Partnership Project 2. , , 2006 . . .

Systems Cisco . . Inc. . . Cisco ASR 5000 Series Aggregation Services Router Installation and Administration Guide Version 10.0 , , 2013 . . .

Y. Go , , , M.A. Jamshed , , , Y. Moon , , , 等 . . APUNet: revitalizing GPU as packet processing accelerator . . Proc. USENIX Symp. on Networked Systems Design and Implementation , , 2017 . . p.83 - - 96 . . . .

S. Han , , , K. Jang , , , K. Park , , , 等 . . PacketShader: a GPU-accelerated software router . . ACM SIGCOMM Comput. Commun. Rev. , , 2010 . . 40 ( ( 4 ): ): 195 - - 206 . . DOI: 10.1145/1851182.1851207 http://doi.org/10.1145/1851182.1851207 . .

Products Intel . . Inc. . . Crystal Forest Platform: Product Overview , , 2010 . . .

Society Internet . . Inc. . . Request For Comments No. 1661. , , 2014 . . .

L. Kekely , , , V. Puš , , , P. Benáček , , , 等 . . Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring . . Proc. 24th Int. Conf. on Field Programmable Logic and Applications , , 2014 . . p.1 - - 4 . . DOI: 10.1109/fpl.2014.6927443 http://doi.org/10.1109/fpl.2014.6927443 . .

M. Lavasani , , , H. Angepat , , , D. Chiou . . An FPGA-based in-line accelerator for memcached . . IEEE Comput. Archit. Lett. , , 2014 . . 13 ( ( 2 ): ): 57 - - 60 . . DOI: 10.1109/l-ca.2013.17 http://doi.org/10.1109/l-ca.2013.17 . .

D. Neil , , , S.C. Liu . . Minitaur, an event-driven FPGAbased spiking network accelerator . . IEEE Trans. VLSI Syst. , , 2014 . . 22 ( ( 12 ): ): 2621 - - 2628 . . DOI: 10.1109/tvlsi.2013.2294916 http://doi.org/10.1109/tvlsi.2013.2294916 . .

M. Peemen , , , A.A. Setio , , , B. Mesman , , , 等 . . Memorycentric accelerator design for convolutional neural networks . . Proc. IEEE 31st Int. Conf. on Computer Design , , 2013 . . p.13 - - 19 . . DOI: 10.1109/iccd.2013.6657019 http://doi.org/10.1109/iccd.2013.6657019 . .

L. Rizzo . . Netmap: a novel framework for fast packet I/O . . Proc. 21st USENIX Security Symp. , , 2012 . . p.101 - - 112 . . . .

M. Vallentin , , , R. Sommer , , , J. Lee , , , 等 . . The NIDS cluster: scalable, stateful network intrusion detection on commodity hardware . . Proc. Int. Workshop on Recent Advances in Intrusion Detection , , 2007 . . p.107 - - 126 . . DOI: 10.1007/978-3-540-74320-0_6 http://doi.org/10.1007/978-3-540-74320-0_6 . .

G. Vasiliadis , , , M. Polychronakis , , , S. Ioannidis . . MIDeA: a multi-parallel intrusion detection architecture . . Proc. 18th ACM Conf. on Computer and Communications Security , , 2011 . . p.297 - - 308 . . DOI: 10.1145/2046707.2046741 http://doi.org/10.1145/2046707.2046741 . .

C. Zhang , , , P. Li , , , G. Sun , , , 等 . . Optimizing FPGAbased accelerator design for deep convolutional neural networks . . Proc. ACM/SIGDA Int. Symp. on FieldProgrammable Gate Arrays , , 2015 . . p.161 - - 170 . . DOI: 10.1145/2684746.2689060 http://doi.org/10.1145/2684746.2689060 . .

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