A BCH error correction scheme applied to FPGA with embedded memory

Yang LIU; Jie LI; Han WANG; Debiao ZHANG; Kaiqiang FENG; Jinqiang LI

doi:10.1631/FITEE.2000323

Your Location：

Home >

Browse articles >

A BCH error correction scheme applied to FPGA with embedded memory

Regular Papers | Updated：2022-05-19

- A BCH error correction scheme applied to FPGA with embedded memory
  Enhanced Publication
- 一种应用于带有嵌入式存储器的FPGA的BCH纠错方案
- Frontiers of Information Technology & Electronic Engineering Vol. 22, Issue 8, Pages: 1127-1139(2021)
- Affiliations：
  
  National Key Laboratory for Electronic Measurement Technology, North University of China, Taiyuan 030051, China
  Shandong Aerospace Electronic Technology Institute, Yantai 264000, China
- Author bio：
  
  Yang LIU, E-mail: lylyly357@163.com
  Jie LI, E-mail: lijie@nuc.edu.cn
- Funds：
- DOI：10.1631/FITEE.2000323
  CLC： TN911
- Published：2021-08，
  
  Received：05 July 2020，
  
  Revised：08 June 2021，
- Accepted：
Scan QR Code
YANG LIU, JIE LI, HAN WANG, et al. A BCH error correction scheme applied to FPGA with embedded memory. [J]. Frontiers of information technology & electronic engineering, 2021, 22(8): 1127-1139.
DOI：

YANG LIU, JIE LI, HAN WANG, et al. A BCH error correction scheme applied to FPGA with embedded memory. [J]. Frontiers of information technology & electronic engineering, 2021, 22(8): 1127-1139. DOI： 10.1631/FITEE.2000323.

摘要

鉴于存储介质上的数据存在位翻转的可能，提出一种模块化的、高速并行的Bose–Chaudhuri–Hocquenghem（BCH）纠错方案，该方案结合了逻辑实现和查找表。所提方案适用于具有片上嵌入式存储器的现场可编程门阵列的数据纠错。详细阐述了系统各部分的优化方法，并分析了该方案在BCH码信息位长度为1024位、码长为1068位且可纠正4位错误情况下的实现过程。

Abstract

Given the potential for bit flipping of data on a memory medium

a high-speed parallel Bose–Chaudhuri–Hocquenghem (BCH) error correction scheme with modular characteristics

combining logic implementation and a look-up table

is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

关键词

纠错算法Bose–Chaudhuri–Hocquenghem (BCH) 码现场可编程门阵列 (FPGA)闪存

Keywords

Error correction algorithmBose–Chaudhuri–Hocquenghem (BCH) codeField programmable gate array (FPGA)NAND flash

references

M Ayinala, , , KK Parhi. . High-speed parallel architectures for linear feedback shift registers. . IEEE Trans Signal Process, , 2011. . 59((9):):4459--4469. . DOI:10.1109/TSP.2011.2159495http://doi.org/10.1109/TSP.2011.2159495..

J Bellorado, , , A Kavcic. . Low-complexity soft-decoding algorithms for Reed–Solomon codes—part Ⅰ: an algebraic soft-in hard-out chase decoder. . IEEE Trans Inform Theory, , 2010. . 56((3):):945--959. . DOI:10.1109/TIT.2009.2039073http://doi.org/10.1109/TIT.2009.2039073..

E Berlekamp. . Algebraic Coding Theory, , ::London, UKWorld Scientific, , 2015. ..

SG Cho, , , D Kim, , , J Choi, , , 等. . Block-wise concatenated BCH codes for NAND flash memories. . IEEE Trans Commun, , 2014. . 62((4):):1164--1177. . DOI:10.1109/TCOMM.2014.021514.130287http://doi.org/10.1109/TCOMM.2014.021514.130287..

GH Hu, , , J Sha, , , ZF Wang. . High-speed parallel LFSR architectures based on improved state-space transformations. . IEEE Trans Very Large Scale Integr Syst, , 2017. . 25((3):):1159--1163. . DOI:10.1109/TVLSI.2016.2608921http://doi.org/10.1109/TVLSI.2016.2608921..

J Jung, , , H Yoo, , , Y Lee, , , 等. . Efficient parallel architecture for linear feedback shift registers. . IEEE Trans Circ Syst Ⅱ, , 2015. . 62((11):):1068--1072. . DOI:10.1109/TCSII.2015.2456294http://doi.org/10.1109/TCSII.2015.2456294..

D Kim, , , KR Narayanan, , , J Ha. . Symmetric block-wise concatenated BCH codes for NAND flash memories. . IEEE Trans Commun, , 2018. . 66((10):):4365--4380. . DOI:10.1109/TCOMM.2018.2839606http://doi.org/10.1109/TCOMM.2018.2839606..

J Kim, , , W Sung. . Low-energy error correction of NAND flash memory through soft-decision decoding. . EURASIP J Adv Signal Process, , 2012. . 2012((1):):195DOI:10.1186/1687-6180-2012-195http://doi.org/10.1186/1687-6180-2012-195..

HP Kumar, , , U Sripati, , , KR Shetty. . High-speed and parallel approach for decoding of binary BCH codes with application to flash memory devices. . Int J Electron, , 2012. . 99((5):):683--693. . DOI:10.1080/00207217.2011.643498http://doi.org/10.1080/00207217.2011.643498..

J Massey. . Shift-register synthesis and BCH decoding. . IEEE Trans Inform Theory, , 1969. . 15((1):):122--127. . DOI:10.1109/TIT.1969.1054260http://doi.org/10.1109/TIT.1969.1054260..

TK Moon. . Error Correction Coding: Mathematical Methods and Algorithms, , ::Hoboken, USAJohn Wiley & Sons, Inc., , 2005. ..

A Neubauer, , , J Freudenberger, , , V Kühn. . Coding Theory: Algorithms, Architectures, and Applications, , ::Chichester, UKJohn Wiley & Sons, Ltd., , 2007. ..

C Paar. . A new architecture for a parallel finite field multiplier with low complexity based on composite fields. . IEEE Trans Comput, , 1996. . 45((7):):856--861. . DOI:10.1109/12.508323http://doi.org/10.1109/12.508323..

KKS Pandian, , , KC Ray. . Five decade evolution of feedback shift register: algorithms, architectures and applications. . Int J Commun Netw Distr Syst, , 2015. . 15((2-3):):279DOI:10.1504/IJCNDS.2015.070974http://doi.org/10.1504/IJCNDS.2015.070974..

TB Pei, , , C Zukowski. . High-speed parallel CRC circuits in VLSI. . IEEE Trans Commun, , 1992. . 40((4):):563--657. . DOI:10.1109/26.141415http://doi.org/10.1109/26.141415..

MD Shieh, , , MH Sheu, , , CH Chen, , , 等. . A systematic approach for parallel CRC computations. . J Inform Sci Eng, , 2001. . 17((3):):445--461. . DOI:10.6688/JISE.2001.17.3.3http://doi.org/10.6688/JISE.2001.17.3.3..

B Unal, , , A Akoglu, , , F Ghaffari, , , 等. . Hardware implementation and performance analysis of resource efficient probabilistic hard decision LDPC decoders. . IEEE Trans Circ Syst I, , 2018. . 65((9):):3074--3084. . DOI:10.1109/TCSI.2018.2815008http://doi.org/10.1109/TCSI.2018.2815008..

FX Xu, , , Y Liu, , , YQ Liu, , , 等. . Design and implementation of mode reconfigurable NAND flash error correcting system. . J Centr South Univ Sci Technol, , 2013. . 44((5):):1918--1925. . ..

CG Yang, , , Y Emre, , , C Chakrabarti. . Product code schemes for error correction in MLC NAND flash memories. . IEEE Trans Very Large Scale Integr Syst, , 2012. . 20((12):):2302--2314. . DOI:10.1109/TVLSI.2011.2174389http://doi.org/10.1109/TVLSI.2011.2174389..

M Zhang, , , F Wu, , , CS Xie. . A novel optimization algorithm for Chien search of BCH codes in NAND flash memory devices. . IEEE Int Conf on Networking, Architecture and Storage, , 2015. . p.106--111. . DOI:10.1109/NAS.2015.7255204http://doi.org/10.1109/NAS.2015.7255204..

XM Zhang. . A low-power parallel architecture for linear feedback shift registers. . IEEE Trans Circ Syst Ⅱ, , 2019. . 66((3):):412--416. . DOI:10.1109/TCSII.2018.2860934http://doi.org/10.1109/TCSII.2018.2860934..

XM Zhang, , , KK Parhi. . High-speed architectures for parallel long BCH encoders. . IEEE Trans Very Large Scale Integr Syst, , 2005. . 13((7):):872--877. . DOI:10.1109/TVLSI.2005.850125http://doi.org/10.1109/TVLSI.2005.850125..

Views

Downloads

CSCD

Alert me when the article has been cited

Submit

Tools

Publicity Resources

No data

Related Author

No data

Related Institution

No data

Address：Zhejiang University Press, 148 Tianmushan Road, Hangzhou, China Postal code：310028
Tel：+86-571-88273162 Email：fitee@zju.edu.cn
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰