An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC

Mengni BIE; Wei LI; Tao CHEN; Longmei NAN; Danyang YANG

doi:10.1631/FITEE.2000325

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An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC

Regular Papers | Updated：2022-04-19

- An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC
  Enhanced Publication
- 一种用于RSA和ECC的高能效可重构非对称密码模运算单元
- Frontiers of Information Technology & Electronic Engineering Vol. 23, Issue 1, Pages: 134-144(2022)
- Affiliations：
  
  1.Information Engineering University, Zhengzhou450001, China
  2.State Key Lab of ASIC and System, Fudan University, Shanghai200000, China
- Author bio：
  
  E-mail: raspberry0213@126.com;
  ‡Corresponding author
- Funds：
- DOI：10.1631/FITEE.2000325
  CLC： TP331.2;TN918.2
- Received：06 July 2020，
  
  Accepted：22 December 2020，
  
  Published：0 January 2022
- Accepted：
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Mengni BIE, Wei LI, Tao CHEN, et al. An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC[J]. Frontiers of Information Technology & Electronic Engineering, 2022, 23(1): 134-144.
DOI：

Mengni BIE, Wei LI, Tao CHEN, et al. An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC[J]. Frontiers of Information Technology & Electronic Engineering, 2022, 23(1): 134-144. DOI： 10.1631/FITEE.2000325.

摘要

RSA和椭圆曲线密码（ECC）算法广泛应用于身份验证、数据安全和访问控制。本文分析了ECC和RSA算法基本操作并对模乘和模逆算法进行优化。提出一个具有混合内存单元和双乘加结构的可重构模运算单元，实现了非对称密码算法在运算单元层次的统一。采用55 nm CMOS标准工艺对模运算单元进行综合，该单元占用硬件资源437 801 μm

，最高时钟频率可达588 MHz。所提模运算单元完成2048位RSA模乘和模逆功耗分别为21.92和23.36 mW，完成512位ECC双域模乘和模逆功耗分别为16.16 和15.88 mW。它比现有单一算法单元更高效、更灵活。与现有多算法单元相比，所提单元表现出更好性能。将所提模运算单元嵌入64位RISC-V处理器，可实现RSA和ECC的密钥生成、加解密以及数字签名功能。实验结果表明，所提设计在

(

)和

)上实现256位ECC点乘分别需要0.224和0.153 ms，实现1024位RSA求幂需要0.96 ms，满足高能效需求。

Abstract

RSA and ellipse curve cryptography (ECC) algorithms are widely used in authentication

data security

and access control. In this paper

we analyze the basic operation of the ECC and RSA algorithms and optimize their modular multiplication and modular inversion algorithms. We then propose a reconfigurable modular operation architecture

with a mix-memory unit and double multiply-accumulate structures

to realize our unified

asymmetric cryptosystem structure in an operational unit. Synthesized with 55-nm CMOS process

our design runs at 588 MHz and requires only 437 801 μm

of hardware resources. Our proposed design takes 21.92 and 23.36 mW for 2048-bit RSA modular multiplication and modular inversion respectively

as well as 16.16 and 15.88 mW to complete 512-bit ECC dual-field modular multiplication and modular inversion respectively. It is more energy-efficient and flexible than existing single algorithm units. Compared with existing multiple algorithm units

our proposed method shows better performance. The operation unit is embedded in a 64-bit RISC-V processor

realizing key generation

encryption and decryption

and digital signature functions of both RSA and ECC. Our proposed design takes 0.224 and 0.153 ms for 256-bit ECC point multiplication in

and

respectively

as well as 0.96 ms to complete 1024-bit RSA exponentiation

meeting the demand for high energy efficiency.

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Keywords

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