Implementation of PRINCE with resource-efficient structures based on FPGAs

Lang LI; Jingya FENG; Botao LIU; Ying GUO; Qiuping LI

doi:10.1631/FITEE.2000688

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Implementation of PRINCE with resource-efficient structures based on FPGAs

Regular Papers | Updated：2022-06-06

- Implementation of PRINCE with resource-efficient structures based on FPGAs
- 基于FPGA的资源节约型结构PRINCE的实现
- Frontiers of Information Technology & Electronic Engineering Vol. 22, Issue 11, Pages: 1505-1516(2021)
- Affiliations：
  
  Hunan Provincial Key Laboratory of Intelligent Information Processing and Application, Hengyang Normal University, Hengyang 421002, China
  College of Information Science and Engineering, Hunan Normal University, Changsha 410081, China
  College of Computer Science and Technology, Hengyang Normal University, Hengyang 421002, China
- Author bio：
  
  [ "Lang LI, E-mail: lilang911@126.com" ]
  Jingya FENG, E-mail: fengjyk@126.com
- Funds：
- DOI：10.1631/FITEE.2000688
  CLC： TP309
- Received：09 December 2020，
  
  Revised：2021-10-12，
  
  Published：2021-11
- Accepted：
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Lang LI, Jingya FENG, Botao LIU, et al. Implementation of PRINCE with resource-efficient structures based on FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(11): 1505-1516.
DOI：

Lang LI, Jingya FENG, Botao LIU, et al. Implementation of PRINCE with resource-efficient structures based on FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(11): 1505-1516. DOI： 10.1631/FITEE.2000688.

摘要

在当今普适计算时代，低资源设备已广泛部署在各个领域。PRINCE是一种专为低延迟设计的轻量级分组密码，适用于普适计算应用程序。本文通过共享和简化逻辑电路为PRINCE组件提出新的电路结构，以达到使用较少逻辑门获得相同效果的目标。基于组件新的电路结构和组件之间的最佳共享，提出3种新的PRINCE硬件架构，并在不同可编程门阵列设备上对3种硬件架构进行仿真和综合。基于Virtex-6平台的实验结果表明，与现有架构相比，展开、低成本和两周期架构的资源消耗分别减少73、119和380个可编程逻辑单元。低成本架构仅需137个可编程逻辑单元。展开架构需409个可编程逻辑单元，其吞吐量为5.34 Gb/s。据我们所知，对于PRINCE的硬件实现，所提低成本架构具有更低资源消耗，且所提展开架构具有更高吞吐量。因此，所提架构具有更高资源效率，适用于低资源、低延迟的应用程序。

Abstract

In this era of pervasive computing

low-resource devices have been deployed in various fields. PRINCE is a lightweight block cipher designed for low latency

and is suitable for pervasive computing applications. In this paper

we propose new circuit structures for PRINCE components by sharing and simplifying logic circuits

to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components

we propose three new hardware architectures for PRINCE. The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures

the resource consumption of the unrolled

low-cost

and two-cycle architectures is reduced by 73

119

and 380 slices

respectively. The low-cost architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge

for the hardware implementation of PRINCE

the new low-cost architecture sets new area records

and the new unrolled architecture sets new throughput records. Therefore

the newly proposed architectures are more resource-efficient and suitable for lightweight

latency-critical applications.

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references

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