An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending<sup>#</sup>

Ayoub SADEGHI; Nabiollah SHIRI; Mahmood RAFIEE; Mahsa TAHGHIGH

doi:10.1631/FITEE.2100432

Your Location：

Home >

Browse articles >

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending^#

Regular Papers | Updated：2022-07-11

- An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending^#
  Enhanced Publication
- 用于图像融合基于混合全加器和计数器的高效华莱士树型乘法器
- Frontiers of Information Technology & Electronic Engineering Vol. 23, Issue 6, Pages: 950-965(2022)
- Affiliations：
  
  Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz71987-74731, Iran
- Author bio：
  
  ‡Corresponding author
- Funds：
- DOI：10.1631/FITEE.2100432
  CLC： TN43
- Published：0 June 2022，
  
  Received：10 September 2021，
  
  Revised：29 December 2021，
- Accepted：
Scan QR Code
AYOUB SADEGHI, NABIOLLAH SHIRI, MAHMOOD RAFIEE, et al. An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending^#. [J]. Frontiers of information technology & electronic engineering, 2022, 23(6): 950-965.
DOI：

AYOUB SADEGHI, NABIOLLAH SHIRI, MAHMOOD RAFIEE, et al. An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending^#. [J]. Frontiers of information technology & electronic engineering, 2022, 23(6): 950-965. DOI： 10.1631/FITEE.2100432.

摘要

提出一种新的基于计数器的华莱士树（CBW）8×8乘法器。乘法器的计数器使用基于传输门技术的新型混合全加器单元。所提全加器、基于传输门的与门和混合半加器生成

:3（4≤

≤7）数字计数器，能够节省至少50%的面积。通过90 nm技术仿真证明所提全加器和数字计数器在不同条件下均优于当前最先进设计。通过使用所提单元，CBW乘法器表现出高驱动、低功耗和高速性能。CBW乘法器在焊盘中的芯片面积为0.0147 mm

。后布局提取证明了实验的准确性。同时提出一种图像融合机制，其中MATLAB和HSPICE之间的直接接口用于在图像处理应用中评估所提CBW乘法器。峰值信噪比和结构相似性指数度量被用作图像质量参数，结果证实所提CBW乘法器可以替代文献中的设计。

Abstract

We present a new counter-based Wallace-tree (CBW) 8×8 multiplier. The multiplier‍’‍s counters are implemented with a new hybrid full adder (FA) cell

which is based on the transmission gate (TG) technique. The proposed FA

TG-based AND gate

and hybrid half adder (HA) generate

:3 (4≤

≤7) digital counters with the ability to save at least 50% area occupation. Simulations by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art designs. By using the proposed cells

the CBW multiplier exhibits high driving capability

low power consumption

and high speed. The CBW multiplier has a 0.0147 mm

die area in a pad. The post-layout extraction proves the accuracy of experimental implementation. An image blending mechanism is proposed

in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing applications. The peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM) are calculated as image quality parameters

and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.

关键词

全加器传输门计数器乘法器三维布局图像融合

Keywords

Full adderTransmission gateCounterMultiplierThree-dimensional layoutImage blending

references

Aguirre-Hernandez M, Linares-Aranda M, 2011. CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans Very Large Scale Integr Syst, 19(4):718-721. https://doi.org/10.1109/tvlsi.2009.2038166https://doi.org/10.1109/tvlsi.2009.2038166

Amini-Valashani M, Ayat M, Mirzakuchaki S, 2018. Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. Microelectr J, 74:49-59. https://doi.org/10.1016/j.mejo.2018.01.018https://doi.org/10.1016/j.mejo.2018.01.018

Asif S, Kong YN, 2015. Design of an algorithmic Wallace multiplier using high speed counters. Proc 10th Int Conf on Computer Engineering & Systems, p.133-138. https://doi.org/10.1109/icces.2015.7393033https://doi.org/10.1109/icces.2015.7393033

Chang CH, Gu JM, Zhang MY, 2004. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Trans Circ Syst I Regul Pap, 51(10):1985-1997. https://doi.org/10.1109/tcsi.2004.835683https://doi.org/10.1109/tcsi.2004.835683

Chowdhury SR, Banerjee A, Roy A, et al., 2008. Design, simulation and testing of a high speed low power 15-4 compressor for high speed multiplication applications. Proc 1st Int Conf on Emerging Trends in Engineering and Technology, p.‍434-438. https://doi.‍org/10.1109/icetet.2008.151https://doi.‍org/10.1109/icetet.2008.151

Fathi A, Mashoufi B, Azizian S, 2020. Very fast, high-performance 5-2 and 7-2 compressors in CMOS process for rapid parallel accumulations. IEEE Trans Very Large Scale Integr Syst, 28(6):1403-1412. https://doi.org/10.1109/tvlsi.2020.2983458https://doi.org/10.1109/tvlsi.2020.2983458

Fritz C, Fam AT, 2017. Fast binary counters based on symmetric stacking. IEEE Trans Very Large Scale Integr Syst, 25(10):2971-2975. https://doi.org/10.1109/tvlsi.2017.2723475https://doi.org/10.1109/tvlsi.2017.2723475

Hasan M, Zaman HU, Hossain M, et al., 2020. Gate diffusion input technique based full swing and scalable 1-bit hybrid full adder for high performance applications. Eng Sci Technol Int J, 23(6):1364-1373. https://doi.org/10.1016/j.jestch.2020.05.008https://doi.org/10.1016/j.jestch.2020.05.008

Jain R, Pandey N, 2021. Approximate Karatsuba multiplier for error-resilient applications. AEU-Int J Electron Commun, 130:53579. https://doi.org/10.1016/j.aeue.2020.153579https://doi.org/10.1016/j.aeue.2020.153579

Kandpal J, Tomar A, Agarwal M, et al., 2020. High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell. IEEE Trans Very Large Scale Integr Syst, 28(6):1413-1422. https://doi.org/10.1109/tvlsi.2020.2983850https://doi.org/10.1109/tvlsi.2020.2983850

Kumar P, Sharma RK, 2016. Low voltage high performance hybrid full adder. Eng Sci Technol Int J, 19(1):559-565. https://doi.org/10.1016/j.jestch.2015.10.001https://doi.org/10.1016/j.jestch.2015.10.001

Luo YS, Liu SI, 2017. A voltage multiplier with adaptive threshold voltage compensation. IEEE J Sol-State Circ, 52(8):2208-2214. https://doi.org/10.1109/jssc.2017.2693228https://doi.org/10.1109/jssc.2017.2693228

Mehrabi S, Mirzaee RF, Zamanzadeh S, et al., 2013. Design, analysis, and implementation of partial product reduction phase by using wide m:‍3 (4≤m≤10) compressors. Int J High Perform Syst Arch, 4(4):231-241. https://doi.org/10.1504/ijhpsa.2013.058986https://doi.org/10.1504/ijhpsa.2013.058986

Momeni A, Han J, Montuschi P, et al., 2015. Design and analysis of approximate compressors for multiplication. IEEE Trans Comput, 64(4):984-994. https://doi.org/10.1109/tc.2014.2308214https://doi.org/10.1109/tc.2014.2308214

Mukherjee B, Ghosal A, 2019. Counter based low power, low latency Wallace tree multiplier using GDI technique for on-chip digital filter applications. Proc Devices for Integrated Circuit, p.151-155. https://doi.org/10.1109/devic.2019.8783456https://doi.org/10.1109/devic.2019.8783456

Naseri H, Timarchi S, 2018. Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Trans Very Large Scale Integr Syst, 26(8):1481-1493. https://doi.org/10.1109/tvlsi.2018.2820999https://doi.org/10.1109/tvlsi.2018.2820999

Ranasinghe AC, Gerez SH, 2020. Glitch-optimized circuit blocks for low-power high-performance booth multipliers. IEEE Trans Very Large Scale Integr Syst, 28(9):2028-2041. https://doi.org/10.1109/tvlsi.2020.3009239https://doi.org/10.1109/tvlsi.2020.3009239

Sadeghi A, Shiri N, Rafiee M, 2020. High-efficient, ultra-low-power and high-speed 4:‍2 compressor with a new full adder cell for bioelectronics applications. Circ Syst Signal Process, 39(12):6247-6275. https://doi.org/10.1007/s00034-020-01459-xhttps://doi.org/10.1007/s00034-020-01459-x

Safaei Mehrabani Y, Eshghi M, 2016. Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology. IEEE Trans Very Large Scale Integr Syst, 24(11):3268-3281. https://doi.org/10.1109/tvlsi.2016.2540071https://doi.org/10.1109/tvlsi.2016.2540071

Saha A, Pal R, Naik AG, et al., 2018. Novel CMOS multi-bit counter for speed-power optimization in multiplier design. AEU-Int J Electron Commun, 95:189-198. https://doi.org/10.1016/j.aeue.2018.08.015https://doi.org/10.1016/j.aeue.2018.08.015

Salmanpour F, Moaiyeri MH, Sabetzadeh F, 2021. Ultra-compact imprecise 4:‍2 compressor and multiplier circuits for approximate computing in deep nanoscale. Circ Syst Signal Process, 40(9):4633-4650. https://doi.org/10.1007/s00034-021-01688-8https://doi.org/10.1007/s00034-021-01688-8

Shiri Asmangerdi N, Forounchi J, Ghanbari K, 2012. A new 8-transistors floating full-adder circuit. Proc 20th Iranian Conf on Electrical Engineering, p.194-197. https://doi.org/10.1109/iraniancee.2012.6292351https://doi.org/10.1109/iraniancee.2012.6292351

Taheri M, Akbar R, Safaei F, et al., 2016. Comparative analysis of adiabatic full adder cells in CNFET technology. Eng Sci Technol Int J, 19(4):2119-2128. https://doi.org/10.1016/j.jestch.2016.08.007https://doi.org/10.1016/j.jestch.2016.08.007

Tirupathireddy A, Sarada M, Srinivasulu A, 2021. Energy-efficient approximate adders for DSP applications. Anal Integr Circ Signal Process, 107(3):649-657. https://doi.org/10.1007/s10470-020-01768-whttps://doi.org/10.1007/s10470-020-01768-w

Tripathi PK, Tripathi JS, Tripathi DS, 2013. Area efficient error compensation circuit for fixed width unsigned multiplier by probabilistic analysis of partial product array. Proc Int Conf on Advances in Technology and Engineering, p.1-4. https://doi.org/10.1109/icadte.2013.6524754https://doi.org/10.1109/icadte.2013.6524754

Veeramachaneni S, Lingamneni A, Krishna MK, et al., 2007. Novel architectures for efficient (m, n) parallel counters. Proc 17th ACM Great Lakes Symp on VLSI, p.188-191. https://doi.org/10.1145/1228784.1228833https://doi.org/10.1145/1228784.1228833

Wallace CS, 1964. A suggestion for a fast multiplier. IEEE Trans Electr Comput, EC-13(1):14-17. https://doi.org/10.1109/pgec.1964.263830https://doi.org/10.1109/pgec.1964.263830

Weste NHE, Eshraghian K, 1993. Principles of CMOS VLSI Design: a Systems Perspective (2nd Ed.). Addison-Wesley Publishing Company, Massachusetts, USA.

Zhuang N, Wu HM, 1992. A new design of the CMOS full adder. IEEE J Sol-State Circ, 27(5):840-844. https://doi.org/10.1109/4.133177https://doi.org/10.1109/4.133177

Views

Downloads

CSCD

Alert me when the article has been cited

Submit

Tools

Publicity Resources

Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study

Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits

A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

Related Author

Mohammad Gholami

Zaman Amirzadeh

Mohammad GHOLAMI

Zaman AMIRZADEH

Hamideh KHAJEHNASIR-JAHROMI

Pooya TORKZADEH

Massoud DOUSTI

Sepehr TABRIZCHI

Related Institution

Department of Electrical Engineering, Faculty of Engineering and Technology, University of Mazandaran, Babolsar

Department of Electrical Engineering, Mazandaran University of Science and Technology, Babol

Department of Electrical Engineering, Faculty of Engineering and Technology, University of Mazandaran

Department of Electrical Engineering, Mazandaran University of Science and Technology

Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University

Address：Zhejiang University Press, 148 Tianmushan Road, Hangzhou, China Postal code：310028
Tel：+86-571-88273162 Email：fitee@zju.edu.cn
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰