Liang WEI, Dan-dan DING, Juan DU, et al. An efficient hardware design for HDTV H.264/AVC encoder[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(6): 499-506.
DOI:
Liang WEI, Dan-dan DING, Juan DU, et al. An efficient hardware design for HDTV H.264/AVC encoder[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(6): 499-506. DOI: 10.1631/jzus.C1000201.
An efficient hardware design for HDTV H.264/AVC encoder
This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance
and design a sharable architecture for normal mode fractional motion estimation (NFME)
special mode fractional motion estimation (SFME)
and luma motion compensation (LMC)
to decrease the hardware cost. Based on these technologies
we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system
which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB
compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.
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