The network-on-chip (NoC) architecture is a main factor affecting the system performance of complicated multi-processor systems-on-chips (MPSoCs). To evaluate the effects of the NoC architectures on communication efficiency

several kinds of techniques have been developed

including various simulators and analytical models. The simulators are accurate but time consuming

especially in large space explorations of diverse network configurations; in contrast

the analytical models are fast and flexible

providing alternative methods for performance evaluation. In this paper

we propose a general analytical model to estimate the communication performance for arbitrary NoCs with wormhole routing and virtual channel flow control. To resolve the inherent dependency of successive links occupied by one packet in wormhole routing

we propose the routing path decomposition approach to generating a series of ordered link categories. Then we use the traditional queuing system to derive the fine-grained transmission latency for each network component. According to our experiments

the proposed analytical model provides a good approximation of the average packet latency to the simulation results

and estimates the network throughput precisely under various NoC configurations and workloads. Also

the analytical model runs about 10

5

times faster than the cycle-accurate NoC simulator. Practical applications of the model including bottleneck detection and virtual channel allocation are also presented.