A floating point conversion algorithm for mixed precision computations

Choon Lih HOO; Sallehuddin Mohamed HARIS; Nik Abdullah Nik MOHAMED

doi:10.1631/jzus.C1200043

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A floating point conversion algorithm for mixed precision computations

Electronic Engineering | Updated：2022-12-09

- A floating point conversion algorithm for mixed precision computations
- A floating point conversion algorithm for mixed precision computations
- Frontiers of Information Technology & Electronic Engineering Vol. 13, Issue 9, Pages: 711-718(2012)
- Affiliations：
  
  Department of Mechanical and Materials Engineering, Universiti Kebangsaan Malaysia, UKM Bangi 43600, Malaysia
- Author bio：
  
  [ "Choon Lih HOO, E-mail:steven85@vlsi.eng.ukm.my" ]
  [ "Sallehuddin Mohamed HARIS, E-mail:salleh@eng.ukm.my" ]
  [ "Nik Abdullah Nik MOHAMED, E-mail:enikkei@eng.ukm.my" ]
- Funds：
- DOI：10.1631/jzus.C1200043
  CLC： TN402
- Received：21 February 2012，
  
  Revised：2012-;8-;3，
  
  Published：2012-09
- Accepted：
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Choon Lih HOO, Sallehuddin Mohamed HARIS, Nik Abdullah Nik MOHAMED. A floating point conversion algorithm for mixed precision computations[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(9): 711-718.
DOI：

Choon Lih HOO, Sallehuddin Mohamed HARIS, Nik Abdullah Nik MOHAMED. A floating point conversion algorithm for mixed precision computations[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(9): 711-718. DOI： 10.1631/jzus.C1200043.

摘要

Abstract

The floating point number is the most commonly used real number representation for digital computations due to its high precision characteristics. It is used on computers and on single chip applications such as DSP chips. Double precision (64-bit) representations allow for a wider range of real numbers to be denoted. However

single precision (32-bit) operations are more efficient. Recently

there has been an increasing interest in mixed precision computations which take advantage of single precision efficiency on 64-bit numbers. This calls for the ability to interchange between the two formats. In this paper

an algorithm that converts floating point numbers from 64- to 32-bit representations is presented. The algorithm was implemented as a Verilog code and tested on field programmable gate array (FPGA) using the Quartus Ⅱ DE2 board and Agilent 16821A portable logic analyzer. Results indicate that the algorithm can perform the conversion reliably and accurately within a constant execution time of 25 ns with a 20 MHz clock frequency regardless of the number being converted.

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references

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