A novel ternary JK flip-flop using the resonant tunneling diode literal circuit

Mi LIN; Ling-ling SUN

doi:10.1631/jzus.C1200214

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A novel ternary JK flip-flop using the resonant tunneling diode literal circuit

Electronic Engineering | Updated：2022-12-09

- A novel ternary JK flip-flop using the resonant tunneling diode literal circuit
- A novel ternary JK flip-flop using the resonant tunneling diode literal circuit
- Frontiers of Information Technology & Electronic Engineering Vol. 13, Issue 12, Pages: 944-950(2012)
- Affiliations：
  
  School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
- Author bio：
  
  [ "Mi LIN, E-mail: linmi@hdu.edu.cn" ]
- Funds：
- DOI：10.1631/jzus.C1200214
  CLC： TN702
- Received：06 June 2012，
  
  Revised：2012-11-12，
  
  Published：2012-12
- Accepted：
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Mi LIN, Ling-ling SUN. A novel ternary JK flip-flop using the resonant tunneling diode literal circuit[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(12): 944-950.
DOI：

Mi LIN, Ling-ling SUN. A novel ternary JK flip-flop using the resonant tunneling diode literal circuit[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(12): 944-950. DOI： 10.1631/jzus.C1200214.

摘要

Abstract

A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes (RTDs). It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation. A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation

and the JK flip-flop also has two optional types of output structure. The design of the ternary RTD JK flip-flop is verified by simulation. The RTD literal circuit is the key design component for achieving various types of multi-valued logic (MVL) flip-flops. It can be converted into ternary D and JK flip-flops

and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships. All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations. This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.

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references

K.S. Berezowski , , , S.B.K. Vrudhula . . Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series . . 8th Euromicro Conf. on Digital System Design—Architectures, Methods and Tools , , 2005 . . p.139 - - 142 . . DOI: 10.1109/DSD.2005.21 http://doi.org/10.1109/DSD.2005.21 . .

K.S. Berezowski , , , S.B.K. Vrudhula . . Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices . . Proc. 37th Int. Symp. on Multiple-Valued Logic , , 2007 . . p.24 - - 30 . . DOI: 10.1109/ISMVL.2007.36 http://doi.org/10.1109/ISMVL.2007.36 . .

M. Bhattacharya , , , S. Kulkarni , , , A. Gonzalez , , , P. Mazumder . . Prototyping Technique for Large-Scale RTD-CMOS Circuits . . IEEE Int. Symp. on Circuits and Systems , , 2000 . . p.635 - - 638 . . . .

T. Ebata , , , U. Omae , , , K. Machida , , , K. Hoshi , , , T. Waho . . Enhancement of Comparator Operation Speed by Using Negative-Differential-Resistance Devices . . Proc. IEEE Int. Symp. on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems , , 2010 . . p.3020 - - 3023 . . DOI: 10.1109/ISCAS.2010.5538003 http://doi.org/10.1109/ISCAS.2010.5538003 . .

A.F. Gonzlez , , , M. Bhattacharya , , , S. Kulkarni , , , P. Mazumder . . CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices . . IEEE J. Sol. State Circ. , , 2001 . . 36 ( ( 6 ): ): 924 - - 932 . . DOI: 10.1109/4.924855 http://doi.org/10.1109/4.924855 . .

W.L. Guo . . Resonant Tunneling Devices and Their Applications . . Science Press, Beijing, China , , 2009 . . p.1 - - 353 . . p.1-46, 232-234, 350-353 . .

G.Q. Hang , , , X.C. Zhou . . Novel CMOS Ternary Flip-Flops Using Double Pass-Transistor Logic . . Int. Conf. on Electric Information and Control Engineering , , 2011 . . p.5978 - - 5981 . . DOI: 10.1109/ICEICE.2011.5778391 http://doi.org/10.1109/ICEICE.2011.5778391 . .

N. Homma , , , K. Saito , , , T. Aoki . . Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor . . Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic , , 2012 . . p.110 - - 115 . . DOI: 10.1109/ISMVL.2012.24 http://doi.org/10.1109/ISMVL.2012.24 . .

J. Lee , , , S. Choi , , , K. Yang . . Implementation of a 4:1 Multiplexing Quantum-Effect IC Based on RTD Circuit Topology . . 10th IEEE Conf. on Nanotechnology , , 2010 . . p.211 - - 213 . . DOI: 10.1109/NANO.2010.5697741 http://doi.org/10.1109/NANO.2010.5697741 . .

X.B. Li . . Digital monolithic integrated circuits based on RTTs . . Micronanoelectr. Technol. , , 2009 . . 46 ( ( 1 ): ): 1 - - 9 . . . .

D.S. Liang , , , K.J. Gan , , , K.Y. Chun . . Frequency Divider Design Using the Λ -Type Negative-Differential-Resistance Circuit . . Proc. 53rd IEEE Int. Midwest Symp. on Circuits and Systems , , 2010 . . p.969 - - 972 . . DOI: 10.1109/MWSCAS.2010.5548795 http://doi.org/10.1109/MWSCAS.2010.5548795 . .

M. Lin , , , Z.Y. Sun , , , J.Z. Shen . . Design of NAND and NOR logic gates based on RTD . . Bull. Sci. Technol. , , 2004 . . 20 ( ( 5 ): ): 434 - - 437 . . . .

M. Lin , , , W.F. Lü , , , L.L. Sun . . Design of ternary NAND and NOR gates based on resonant tunneling devices . . J. Semicond. , , 2007 . . 28 ( ( 12 ): ): 1983 - - 1987 . . . .

M. Lin , , , W.F. Lü , , , L.L. Sun . . Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit . . J. Zhejiang Univ.-Sci. C (Comput. & Electron.) , , 2011a . . 12 ( ( 6 ): ): 507 - - 514 . . DOI: 10.1631/jzus.C1000222 http://doi.org/10.1631/jzus.C1000222 . .

M. Lin , , , H.P. Zhang , , , L.L. Sun . . Testability Design of Multi-valued RTD Circuits . . Int. Conf. on Electronics, Communications and Control , , 2011b . . p.510 - - 513 . . DOI: 10.1109/ICECC.2011.6067730 http://doi.org/10.1109/ICECC.2011.6067730 . .

J. Núñez , , , J.M. Quintana , , , M.J. Avedillo . . Correct DC Operation in RTD-Based Ternary Inverters . . Proc. 2nd IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems , , 2007 . . p.860 - - 865 . . DOI: 10.1109/NEMS.2007.352154 http://doi.org/10.1109/NEMS.2007.352154 . .

J. Núñez , , , J.M. Quintana , , , M.J. Avedillo . . Design of RTD-Based NMIN/NMAX Gates . . 8th IEEE Conf. on Nanotechnology , , 2008 . . p.518 - - 521 . . DOI: 10.1109/NANO.2008.155 http://doi.org/10.1109/NANO.2008.155 . .

T. Sasao . . Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation . . Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic , , 2012 . . p.185 - - 190 . . DOI: 10.1109/ISMVL.2012.21 http://doi.org/10.1109/ISMVL.2012.21 . .

S. Suzuki , , , K. Hinata , , , M. Shiraishi , , , M. Asada , , , H. Sugiyama , , , H. Yokoyama . . RTD Oscillators at 430-460 GHz with High Output Power (~200 μW) Using Integrated Offset Slot Antennas . . Int. Conf. on Indium Phosphide and Related Materials , , 2010 . . p.152 - - 155 . . DOI: 10.1109/ICIPRM.2010.5516019 http://doi.org/10.1109/ICIPRM.2010.5516019 . .

T. Uemura , , , T. Baba . . Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop . . Proc. 30th IEEE Int. Symp. on Multiple-Valued Logic , , 2000 . . p.305 - - 310 . . DOI: 10.1109/ISMVL.2000.848636 http://doi.org/10.1109/ISMVL.2000.848636 . .

H.X. Wu , , , S.N. Zhong , , , Q.L. Cai , , , Q.B. Xia , , , Y.Y. Chen . . Design of quaternary logic circuits based on multiple-valued current mode . . Lect. Notes Electr. Eng. , , 2012 . . 138 479 - - 488 . . DOI: 10.1007/978-1-4471-2467-2_56 http://doi.org/10.1007/978-1-4471-2467-2_56 . .

X.W. Wu . . The Design Theory of Multiple Logic Circuits , , : : Hangzhou University Press Hangzhou, China , , 1994 . . p.18 - - 261 . . p.18-43, 233-261 . .

X.W. Wu , , , D.X. Bi . . Research of the ternary flip-flop based on the module algebra . . Acta Electron. Sin. , , 1984 . . 12 ( ( 3 ): ): 6 - - 13 . . . .

Y. Yuminaka , , , M. Okui . . Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation . . Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic , , 2012 . . p.7 - - 12 . . DOI: 10.1109/ISMVL.2012.56 http://doi.org/10.1109/ISMVL.2012.56 . .

W.C. Zhang , , , N.J. Wu . . Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs . . Electron. Lett. , , 2008 . . 44 ( ( 16 ): ): 968 - - 969 . . DOI: 10.1049/el:20080507 http://doi.org/10.1049/el:20080507 . .

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Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit

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Wei-feng LÜ

Ling-ling SUN

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Department of Information Science and Electronic Engineering, Zhejiang University

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