High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding

Kai HUANG; De MA; Rong-jie YAN; Hai-tong GE; Xiao-lang YAN

doi:10.1631/jzus.C1200250

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High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding

Electronic Engineering | Updated：2022-12-09

- High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding
- High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding
- Frontiers of Information Technology & Electronic Engineering Vol. 14, Issue 6, Pages: 449-463(2013)
- Affiliations：
  
  1.Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
  2.State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences, Beijing 100190, China
  3.Hangzhou C-Sky Micro-System Company, Hangzhou 310012, China
- Author bio：
  
  [ "Kai HUANG, E-mail: huangk@vlsi.zju.edu.cn" ]
  Rong-jie YAN, yrj@ios.ac.cn
- Funds：
- DOI：10.1631/jzus.C1200250
  CLC： TN919.8
- Received：28 August 2012，
  
  Revised：2013-;5-13，
  
  Published：2013-06
- Accepted：
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Kai HUANG, De MA, Rong-jie YAN, et al. High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding[J]. Frontiers of Information Technology & Electronic Engineering, 2013, 14(6): 449-463.
DOI：

Kai HUANG, De MA, Rong-jie YAN, et al. High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding[J]. Frontiers of Information Technology & Electronic Engineering, 2013, 14(6): 449-463. DOI： 10.1631/jzus.C1200250.

摘要

Abstract

Context-based adaptive binary arithmetic coding (CABAC) is the major entropy-coding algorithm employed in H.264/AVC. In this paper

we present a new VLSI architecture design for an H.264/AVC CABAC decoder

which optimizes both decode decision and decode bypass engines for high throughput

and improves context model allocation for efficient external memory access. Based on the fact that the most possible symbol (MPS) branch is much simpler than the least possible symbol (LPS) branch

a newly organized decode decision engine consisting of two serially concatenated MPS branches and one LPS branch is proposed to achieve better parallelism at lower timing path cost. A look-ahead context index (ctxIdx) calculation mechanism is designed to provide the context model for the second MPS branch. A head-zero detector is proposed to improve the performance of the decode bypass engine according to UEGk encoding features. In addition

to lower the frequency of memory access

we reorganize the context models in external memory and use three circular buffers to cache the context models

neighboring information

and bit stream

respectively. A pre-fetching mechanism with a prediction scheme is adopted to load the corresponding content to a circular buffer to hide external memory latency. Experimental results show that our design can operate at 250 MHz with a 20.71k gate count in SMIC18 silicon technology

and that it achieves an average data decoding rate of 1.5 bins/cycle.

关键词

Keywords

references

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