Novel serpentine structure design method considering confidence level and estimation precision

Li-sheng CHEN; Xiao-hua LUO; Jiao-jiao ZHU; Fan-chao JIE; Xiao-lang YAN

doi:10.1631/jzus.C1200297

Your Location：

Home >

Browse articles >

Novel serpentine structure design method considering confidence level and estimation precision

Electrical & Electronic Engineering | Updated：2022-12-09

- Novel serpentine structure design method considering confidence level and estimation precision
- Novel serpentine structure design method considering confidence level and estimation precision
- Frontiers of Information Technology & Electronic Engineering Vol. 14, Issue 3, Pages: 222-234(2013)
- Affiliations：
  
  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
- Author bio：
  
  Xiao-hua LUO, E-mail: luoxh@vlsi.zju.edu.cn
- Funds：
- DOI：10.1631/jzus.C1200297
  CLC： TN4
- Received：17 October 2012，
  
  Revised：2013-;2-25，
  
  Published：2013-03
- Accepted：
Scan QR Code
Li-sheng CHEN, Xiao-hua LUO, Jiao-jiao ZHU, et al. Novel serpentine structure design method considering confidence level and estimation precision[J]. Frontiers of Information Technology & Electronic Engineering, 2013, 14(3): 222-234.
DOI：

Li-sheng CHEN, Xiao-hua LUO, Jiao-jiao ZHU, et al. Novel serpentine structure design method considering confidence level and estimation precision[J]. Frontiers of Information Technology & Electronic Engineering, 2013, 14(3): 222-234. DOI： 10.1631/jzus.C1200297.

摘要

Abstract

Due to the importance of metal layers in the product yield

serpentine test structures are usually fabricated on test chips to extract parameters for yield prediction. In this paper

the confidence level and estimation precision of the average defect density on metal layers are investigated to minimize the randomness of experimental results and make the measured parameters more convincing. On the basis of the Poisson yield model

the method to determine the total area of all serpentine test structures is obtained using the law of large numbers and the Lindeberg-Levy theorem. Furthermore

the method to determine an adequate area of each serpentine test structure is proposed under a specific requirement of confidence level and estimation precision. The results of Monte Carlo simulation show that the proposed method is consistent with theoretical analyses. It is also revealed by wafer experimental results that the method of designing serpentine test structure proposed in this paper has better performance.

关键词

Keywords

references

D. Arumi , , , R. Rodriguez-Montanes , , , J. Figueras . . Experimental characterization of CMOS interconnect open defects . . IEEE Trans. CAD Integr. Circ. Syst. , , 2008 . . 27 ( ( 1 ): ): 123 - - 136 . . DOI: 10.1109/tcad.2007.907255 http://doi.org/10.1109/tcad.2007.907255 . .

P. Billingsley . . The Lindeberg-Levy theorem for martingales . . Proc. Am. Math. Soc. , , 1961 . . 12 ( ( 5 ): ): 788 - - 792 . . DOI: 10.2307/2034876 http://doi.org/10.2307/2034876 . .

F. Chen , , , M. Shinosky , , , B. Li , , , J. Aitken , , , S. Cohen , , , G. Bonilla , , , A. Simon , , , P. McLaughlin , , , R. Achanta , , , F. Baumann , , , 等 . . Invasion Percolation Model for Abnormal TDDB Characteristic of ULK Dielectrics with Cu Interconnect at Advanced Technology Nodes . . IEEE Int. Conf. on Reliability Physics Symp. , , 2011 . . p.2F.2.1 - - 2F.2.8 . . DOI: 10.1109/irps.2011.5784466 http://doi.org/10.1109/irps.2011.5784466 . .

M. Fayolle , , , P. Gayet , , , Y. Morand . . Multilevel Test Structures for Metal CMP Integration Application to Cu/SiO2 Damascene Interconnect . . 3rd Annual Int. Interconnect Technology Conf. , , 2000 . . p.28 - - 30 . . DOI: 10.1109/iitc.2000.854271 http://doi.org/10.1109/iitc.2000.854271 . .

D.C. Gert , , , M. Enrique . . Weak and strong laws of large numbers for coherent lower previsions . . J. Stat. Plan. Inf. , , 2008 . . 138 ( ( 8 ): ): 2409 - - 2432 . . DOI: 10.1016/j.jspi.2007.10.020 http://doi.org/10.1016/j.jspi.2007.10.020 . .

C. Hess , , , M. Saadat , , , A. Inani , , , L. Yun , , , H. Matsuhashi , , , M. Squicciarini , , , R. Lindley , , , N. Akiya , , , E.F. Kaste . . Yield Improvement Using a Fast Product Wafer Level Monitoring System . . IEEE/SEMI Advanced Semiconductor Manufacturing Conf. and Workshop , , 2006 . . p.417 - - 422 . . DOI: 10.1109/ASMC.2006.1638794 http://doi.org/10.1109/ASMC.2006.1638794 . .

C. Hess , , , A. Inani , , , A. Joag , , , Z. Sa , , , M. Spinelli , , , M. Zaragoza , , , N. Long , , , B. Kumar . . Stackable Short Flow Characterization Vehicle Test Chip to Reduce Test Chip Designs, Mask Cost and Engineering Wafers . . IEEE/ SEMI Conf. on Advanced Semiconductor Manufacturing , , 2010 . . p.328 - - 333 . . DOI: 10.1109/asmc.2010.5551474 http://doi.org/10.1109/asmc.2010.5551474 . .

C.L. Hsu , , , J.Y. Fang , , , A. Yu , , , J. Lin , , , C. Huang , , , J.Y. Wu , , , D.C. Perng . . Defect Study of Manufacturing Feasible Porous Low k Dielectrics Direct Polish for 45 nm Technology and Beyond . . IEEE Int. Interconnect Technology Conf. , , 2009 . . p.140 - - 142 . . DOI: 10.1109/iitc.2009.5090365 http://doi.org/10.1109/iitc.2009.5090365 . .

T.Y. Jeong , , , S.M. Choi , , , D.C. Baek , , , S. Windu , , , M. Lee , , , J. Park . . Effective Line Length of Test Structure and OTS Effect of Area Scaling on TDDB Characterization in Advanced Cu/ULK Process . . IEEE Int. Reliability Physics Symp. , , 2012 . . p.BD.3.1 - - BD.3.4 . . DOI: 10.1109/irps.2012.6241877 http://doi.org/10.1109/irps.2012.6241877 . .

M. Karthikeyan , , , L. Medina , , , E. Shiling , , , D. Kiesling . . 32 nm Yield Learning Using Efficient Parallel-Test Structures . . IEEE/SEMI Advanced Semiconductor Manufacturing Conf. , , 2010 . . p.1 - - 6 . . DOI: 10.1109/asmc.2010.5551411 http://doi.org/10.1109/asmc.2010.5551411 . .

J. Khare , , , W. Maly , , , S. Griep , , , D. Schmitt-Landsiedel . . SRAM-Based Extraction of Defect Characteristics . . Int. Conf. on Microelectronic Test Structures , , 1994 . . p.98 - - 107 . . DOI: 10.1109/ICMTS.1994.303494 http://doi.org/10.1109/ICMTS.1994.303494 . .

N. Konno . . Quantum random walks in one dimension . . Quantum Inf. Process. , , 2002 . . 1 ( ( 5 ): ): 345 - - 354 . . DOI: 10.1023/a:1023413713008 http://doi.org/10.1023/a:1023413713008 . .

M.V. Kumar , , , W. Lukaszek , , , J.D. Plummer . . A test structure advisor and a coupled, library-based test structure layout and testing environment . . IEEE Trans. Semiconduct. Manuf. , , 1997 . . 10 ( ( 3 ): ): 370 - - 383 . . DOI: 10.1109/66.618210 http://doi.org/10.1109/66.618210 . .

C.S. Lin , , , J.H. Huang , , , S.R. Hong , , , C.S. Lo , , , L.S. Chuang . . Integration HDP CVD Oxide Sputtering Effect for Metal Void Defect Solution . . Semiconductor Manufacturing Technology Workshop , , 2002 . . p.165 - - 168 . . DOI: 10.1109/smtw.2002.1197400 http://doi.org/10.1109/smtw.2002.1197400 . .

T.M.Z. Lin , , , W.M. Hsu , , , S.R. Lin , , , R.C.J. Wang , , , C.C. Chiu , , , K. Wu . . Identification and Layout Modification of Copper/Low k Interconnect Dielectric Reliability Assessment by Using RVDB Test . . 44th Annual IEEE Int. Reliability Physics Symp. , , 2006 . . p.687 - - 688 . . DOI: 10.1109/relphy.2006.251325 http://doi.org/10.1109/relphy.2006.251325 . .

X.H. Luo , , , L.S. Chen , , , J.J. Zhu , , , X.L. Yan . . A new via chain design method considering confidence level and estimation precision . . J. Zhejiang Univ.-Sci. C (Comput. & Electron.) , , 2012 . . 13 ( ( 9 ): ): 702 - - 710 . . DOI: 10.1631/jzus.C1200079 http://doi.org/10.1631/jzus.C1200079 . .

T.L. Michalka , , , W. Lukaszek , , , J.D. Meindl . . A redundant metal-polyimide thin film interconnection process for wafer scale dimensions . . IEEE Trans. Semic. Manuf. , , 1990 . . 3 ( ( 4 ): ): 158 - - 167 . . DOI: 10.1109/66.61964 http://doi.org/10.1109/66.61964 . .

D.C. Montgomery , , , G.C. Runger . . Applied Statistics and Probability for Engineers (3rd Ed.) , , : : New York John Wiley & Sons, Inc. , , 2002 . . p.356 - - 359 . . . .

W.J. Roesch , , , D.J.M. Hamada . . Studying Yield and Reliability Relationships for Metal Defects . . Workshop on Reliability of Compound Semiconductors , , 2004 . . p.121 - - 133 . . DOI: 10.1109/rocs.2004.184353 http://doi.org/10.1109/rocs.2004.184353 . .

H.R. Sayah , , , M.G. Buehler . . Comb/Serpentine/ Cross-Bridge Test Structure for Fabrication Process Evaluation . . IEEE Int. Conf. on Microelectronic Test Structures , , 1988 . . p.23 - - 28 . . DOI: 10.1109/icmts.1988.672923 http://doi.org/10.1109/icmts.1988.672923 . .

C.H. Stapper . . Defect density distribution for LSI yield calculations . . IEEE Trans. Electron Dev. , , 1973 . . 20 ( ( 7 ): ): 655 - - 657 . . DOI: 10.1109/T-ED.1973.17719 http://doi.org/10.1109/T-ED.1973.17719 . .

C.H. Stapper . . Modeling of integrated circuit defect sensitivities . . IBM J. Res. Devel. , , 1983 . . 27 ( ( 6 ): ): 549 - - 557 . . DOI: 10.1147/rd.276.0549 http://doi.org/10.1147/rd.276.0549 . .

C.H. Stapper . . Modeling of defects in integrated circuit photolithographic patterns . . IBM J. Res. Devel. , , 1984 . . 28 ( ( 4 ): ): 461 - - 475 . . DOI: 10.1147/rd.284.0461 http://doi.org/10.1147/rd.284.0461 . .

Y. Tamaki , , , M. Ito , , , Y. Takimoto , , , M. Hashino , , , Y. Kawamoto . . New Test Structure for Evaluating Low-k Dielectric Interconnect Layers by Using Ring-Oscillators and Metal Comb/Serpentine Patterns . . 24th IEEE Int. Conf. on Microelectronic Test Structures , , 2011 . . p.125 - - 129 . . DOI: 10.1109/icmts.2011.5976873 http://doi.org/10.1109/icmts.2011.5976873 . .

W.H. Teh , , , L. Guo , , , R. Kumar , , , D.L. Kwong . . 200-mm wafer-scale transfer of 0 . . 18 ǌm dual-damascene Cu/SiO2 interconnection system to plastic substrates. IEEE Electron Dev. Lett. , , 2005 . . 26 ( ( 11 ): ): 802 - - 804 . . DOI: 10.1109/led.2005.857734 http://doi.org/10.1109/led.2005.857734 . .

Y.A. Wahab , , , A.F. Ahmad , , , Z. Awang . . Comparison of Missing Metal Defect Formation on He In-Situ and Furnace Annealed Electroplated Copper Films . . 4th Student Conf. on Research and Development , , 2006 . . p.53 - - 57 . . DOI: 10.1109/scored.2006.4339307 http://doi.org/10.1109/scored.2006.4339307 . .

J.T. Wallmark . . Design considerations for integrated electronic devices . . Proc. IRE , , 1960 . . 48 ( ( 3 ): ): 293 - - 300 . . DOI: 10.1109/JRPROC.1960.287597 http://doi.org/10.1109/JRPROC.1960.287597 . .

B.L. Welch . . The generalization of nstudentoso problem when several different population variances are involved . . Biometrika , , 1947 . . 34 ( ( 1-2 ): ): 28 - - 35 . . DOI: 10.2307/2332510 http://doi.org/10.2307/2332510 . .

Views

Downloads

CSCD

Alert me when the article has been cited

Submit

Tools

Publicity Resources

A new via chain design method considering confidence level and estimation precision

Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process

Related Author

Li-sheng CHEN

Yi YE

Related Institution

No data

Chat

Address：Zhejiang University Press, 148 Tianmushan Road, Hangzhou, China Postal code：310028
Tel：+86-571-88273162 Email：fitee@zju.edu.cn
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰