High-speed, fixed-latency serial links with Xilinx FPGAs

Xue LIU; Qing-xu DENG; Bo-ning HOU; Ze-ke WANG

doi:10.1631/jzus.C1300249

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High-speed, fixed-latency serial links with Xilinx FPGAs

Electronic Engineering | Updated：2022-05-19

- High-speed, fixed-latency serial links with Xilinx FPGAs
- High-speed, fixed-latency serial links with Xilinx FPGAs
- Frontiers of Information Technology & Electronic Engineering Vol. 15, Issue 2, Pages: 153-160(2014)
- Affiliations：
  
  1.Institute of Cyber-Physical System Engineering, Northeastern University, Shenyang 110004, China
  2.Institute of Digital Technology and Instruments, Zhejiang University, Hangzhou 310027, China
- Author bio：
  
  [ "Xue LIU, liuxue0512@gmail.com" ]
  Qing-xu DENG, dengqx@mail.neu.edu.cn
- Funds：
- DOI：10.1631/jzus.C1300249
  CLC： TN79
- Received：11 September 2013，
  
  Revised：2014-1-15，
  
  Accepted：18 December 2013，
  
  Published：2014-02
- Accepted：
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Xue LIU, Qing-xu DENG, Bo-ning HOU, et al. High-speed, fixed-latency serial links with Xilinx FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2014, 15(2): 153-160.
DOI：

Xue LIU, Qing-xu DENG, Bo-ning HOU, et al. High-speed, fixed-latency serial links with Xilinx FPGAs[J]. Frontiers of Information Technology & Electronic Engineering, 2014, 15(2): 153-160. DOI： 10.1631/jzus.C1300249.

摘要

Abstract

High-speed

fixed-latency serial links find application in distributed data acquisition and control systems

such as the timing trigger and control (TTC) system for high energy physics experiments. However

most high-speed serial transceivers do not keep the same chip latency after each power-up or reset

as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper

we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs). First

we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second

we use the internal alignment circuit of the transceiver and a digital clock manager (DCM)/phase-locked loop (PLL) based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions

our design not only implements fixed chip latency

but also reduces the average system lock time.

关键词

Keywords

references

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