用于低电压下SRAM灵敏放大器工艺变化鲁棒性时序的多级双复制位线延迟技术

TAN Shou-biao; LU Wen-juan; PENG Chun-yu; LI Zheng-ping; TAO You-wu; CHEN Jun-ning

doi:10.1631/FITEE.1400439

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用于低电压下SRAM灵敏放大器工艺变化鲁棒性时序的多级双复制位线延迟技术

电气与电子工程 | Updated：2022-06-14

- 用于低电压下SRAM灵敏放大器工艺变化鲁棒性时序的多级双复制位线延迟技术
- Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
- 信息与电子工程前沿（英文） 2015年16卷第8期页码：700-706
- Affiliations：
  
  School of Electronics and Information Engineering, Anhui University, Hefei 230601, China
- Author bio：
  
  [ "Shou-biao TAN, E-mail: tsb@ustc.edu" ]
  [ "Wen-juan LU, E-mail: luwenjuan@yeah.net" ]
  Chun-yu PENG, E-mail: cyupeng@ahu.edu.cn
- Funds：
  
  Project supported by the National Natural Science Foundation of China (No. 61474001)
- DOI：10.1631/FITEE.1400439
  中图分类号： TN43
- 收稿：2014-12-28，
  
  修回：2015-07-20，
  
  纸质出版：2015-08
- Accepted：
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用于低电压下SRAM灵敏放大器工艺变化鲁棒性时序的多级双复制位线延迟技术[J]. 信息与电子工程前沿（英文）, 2015,16(8):700-706.

TAN Shou-biao, LU Wen-juan, PENG Chun-yu, et al. Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier[J]. Frontiers of Information Technology & Electronic Engineering, 2015, 16(8): 700-706.
用于低电压下SRAM灵敏放大器工艺变化鲁棒性时序的多级双复制位线延迟技术[J]. 信息与电子工程前沿（英文）, 2015,16(8):700-706. DOI： 10.1631/FITEE.1400439.

TAN Shou-biao, LU Wen-juan, PENG Chun-yu, et al. Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier[J]. Frontiers of Information Technology & Electronic Engineering, 2015, 16(8): 700-706. DOI： 10.1631/FITEE.1400439.

摘要

目的

针对低电压下传统SRAM灵敏放大器控制时序受工艺、温度变化而引起的较大的控制时序的波动，设计一种基于多级双复制位线延迟技术的控制时序产生电路。

创新点

同时采用多级和双复制位线技术，充分发挥两者在降低控制时序变化方面的优点，取得整体上的改进。

方法

首先，分析现有复制位线延迟技术，从统计学角度对各技术之间的关系进行分析，进而提出一种基于多级双复制位线延迟技术的控制时序产生电路（图5）。然后，针对所提电路与现有技术在最差条件下进行蒙特卡洛仿真对比，得出所提技术在最差工作条件下，与现有技术相比具有更好的鲁棒性（图8）。最后在电压、工艺角以及温度分别变化时，对所提电路设计与现有的电路进行性能对比

得出在工艺、电压及温度变化时，所提电路具有更好的稳定性（图9-11）。

结论

针对低电压SRAM灵敏放大器控制时序在工艺、电压以及温度变化产生的波动，提出一种多级双复制位线延迟技术，实现进一步降低灵敏放大器控制时序波动的效果。

Abstract

A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique

this strategy

using statistical theory

reduces the timing variation by using multi-stage ideas

meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V

the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%

respectively

smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company

Taiwan).

关键词

Keywords

references

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