一种基于参数扰动的芯片成品率双目标优化框架

Xin LI; Jin SUN; Fu XIAO; Jiang-shan TIAN

doi:10.1631/FITEE.1500168

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一种基于参数扰动的芯片成品率双目标优化框架

常规文章 | Updated：2022-05-19

- 一种基于参数扰动的芯片成品率双目标优化框架
- An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations
- 信息与电子工程前沿（英文） 2016年17卷第2期页码：160-172
- Affiliations：
  
  1Technology Innovation Center, Jiangsu Academy of Safety Science and Technology, Nanjing 210042, China
  2Jiangsu High Technology Research Key Laboratory for Wireless Sensor Networks, Nanjing University of Posts and Telecommunications, Nanjing 210013, China
  3School of Computer Science and Engineering, Nanjing University of Science and Technology, Nanjing 210094, China
- Author bio：
  
  E-mail: lin65002@hotmail.com
- Funds：
- DOI：10.1631/FITEE.1500168
  中图分类号： TP312
- 收稿：2015-05-25，
  
  录用：2015-8-24，
  
  纸质出版：2016-02
- Accepted：
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一种基于参数扰动的芯片成品率双目标优化框架[J]. 信息与电子工程前沿（英文）, 2016,17(2):160-172.

Xin LI, Jin SUN, Fu XIAO, et al. An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(2): 160-172.
一种基于参数扰动的芯片成品率双目标优化框架[J]. 信息与电子工程前沿（英文）, 2016,17(2):160-172. DOI： 10.1631/FITEE.1500168.

Xin LI, Jin SUN, Fu XIAO, et al. An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(2): 160-172. DOI： 10.1631/FITEE.1500168.

摘要

目的

基于工艺参数扰动及环境参数扰动，实现对芯片漏电功耗成品率及芯片时延成品率的双目标优化，得到分布均匀的帕累托优化解集。

创新点

考虑分布不确定的工艺参数扰动及环境参数扰动，在任意相关性下利用CAA理论对漏电功耗成品率及芯片时延成品率进行有效估算，降低计算复杂度，并根据AWS方法对漏电功耗成品率及芯片时延成品率同时进行优化，取得了分布均匀的优化解，便于设计人员灵活选择优化解。

方法

首先，考虑工艺参数及环境参数的扰动不确定性，提出一种能够处理任意相关性的漏电功耗及芯片时延概率分布边界估算方法。然后，通过计算累积分布边界构造功耗-时延成品率双目标优化模型。最后，利用AWS方法同时优化漏电功耗成品率及芯片时延成品率，得到一组分布均匀的帕累托优化解，进而提供漏电功耗成品率与芯片时延成品率间的均衡优化信息。

结论

针对工艺参数及环境参数的扰动不确定性，提出了一种能够处理任意相关性的芯片成品率双目标优化算法，得到了一组分布均匀的帕累托优化解。

Abstract

With shrinking technology

the increase in variability of process

voltage

and temperature (PVT) parameters significantly impacts the yield analysis and optimization for chip designs. Previous yield estimation algorithms have been limited to predicting either timing or power yield. However

neglecting the correlation between power and delay will result in significant yield loss. Most of these approaches also suffer from high computational complexity and long runtime. We suggest a novel bi-objective optimization framework based on Chebyshev affine arithmetic (CAA) and the adaptive weighted sum (AWS) method. Both power and timing yield are set as objective functions in this framework. The two objectives are optimized simultaneously to maintain the correlation between them. The proposed method first predicts the guaranteed probability bounds for leakage and delay distributions under the assumption of arbitrary correlations. Then a power-delay bi-objective optimization model is formulated by computation of cumulative distribution function (CDF) bounds. Finally

the AWS method is applied for power-delay optimization to generate a well-distributed set of Pareto-optimal solutions. Experimental results on ISCAS benchmark circuits show that the proposed bi-objective framework is capable of providing sufficient trade-off information between power and timing yield.

关键词

Keywords

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