基于驻波振荡器的PLL设计与仿真

Wei ZHANG; You-de HU; Li-rong ZHENG

doi:10.1631/FITEE.1500210

Your Location：

Home >

Browse articles >

基于驻波振荡器的PLL设计与仿真

常规文章 | Updated：2022-05-19

- 基于驻波振荡器的PLL设计与仿真
  Enhanced Publication
- Design and simulation of a standing wave oscillator based PLL
- 信息与电子工程前沿（英文） 2016年17卷第3期页码：258-264
- Affiliations：
  
  1State Key Lab of ASIC & System, Fudan University, Shanghai 200433, China
  2Pack Vinn Excellence Center, School of ICT, Royal Institute of Technology (KTH) Eletrum 229, Kista-Stockholm 16440, Sweden
- Author bio：
  
  E-mail:wei_zhang@fudan.edu.cn
- Funds：
- DOI：10.1631/FITEE.1500210
  中图分类号： TN432
- 纸质出版日期：2016-03，
  
  收稿日期：2015-06-06，
  
  录用日期：2015-11-18
- Accepted：
Scan QR Code
基于驻波振荡器的PLL设计与仿真[J]. 信息与电子工程前沿（英文）, 2016,17(3):258-264.

WEI ZHANG, YOU-DE HU, LI-RONG ZHENG. Design and simulation of a standing wave oscillator based PLL. [J]. Frontiers of information technology & electronic engineering, 2016, 17(3): 258-264.
基于驻波振荡器的PLL设计与仿真[J]. 信息与电子工程前沿（英文）, 2016,17(3):258-264. DOI： 10.1631/FITEE.1500210.

WEI ZHANG, YOU-DE HU, LI-RONG ZHENG. Design and simulation of a standing wave oscillator based PLL. [J]. Frontiers of information technology & electronic engineering, 2016, 17(3): 258-264. DOI： 10.1631/FITEE.1500210.

摘要

目的

基于标准CMOS工艺实现频率可调节驻波振荡器结构，研究该结构在高性能微处理器中的应用方式并实现基于该结构的PLL设计。

创新点

分析了反型MOS管可变电容在驻波振荡器中不同分布方式对频率调节范围和功耗的影响，根据分析结果设计了基于频率可调节驻波振荡器的PLL。该PLL不仅实现了50%的时钟调节范围，而且可以作为时钟分布网络直接应用于多核处理器结构中。

方法

首先分析了不同阈值对反型MOS管可变电容的影响（图3），提出了基于该可变电容结构的两类驻波振荡器频率调节方式（图4），通过仿真对比分析了两者频率调节和功耗的差异（图5、6）。然后基于分析结果设计了基于频率可调节驻波振荡器的PLL（图7），分析了该PLL的频率锁定过程（图9）。最后分析了该PLL在高性能微处理器设计中的应用方式（图11）。

结论

采用反型MOS管可变电容可实现频率可调节驻波振荡器结构，基于该驻波振荡器可以设计频率调节范围达到50%的PLL，满足高性能微处理器对时钟的要求。

Abstract

A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However

it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor

and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO

a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source

but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9M complementary metal-oxide-semiconductor (CMOS) technology

and can be used directly in a high performance multi-core microprocessor.

关键词

驻波振荡器时钟分布可变电容变抗器

Keywords

Standing wave oscillator (SWO)Clock distributionPhase locked loop (PLL)Varactor

references

W Andress, , , D Ham. . Recent developments in standing-wave oscillator design: review. . 2004. . Radio Frequency Integrated Circuits Symp. . p.119--122. . DOI:10.1109/RFIC.2004.1320545http://doi.org/10.1109/RFIC.2004.1320545..

W Andress, , , D Ham. . Standing wave oscillators utilizing wave-adaptive tapered transmission lines. . IEEE J. Sol.-State Circ., , 2005. . 40((3):):638--651. . DOI:10.1109/JSSC.2005.843600http://doi.org/10.1109/JSSC.2005.843600..

S.C Chan, , , K.L Shepard, , , P.J Restle. . Design of resonant global clock distributions. . 2003. . 21st Int. Conf. on Computer Design. . p.248--253. . DOI:10.1109/ICCD.2003.1240902http://doi.org/10.1109/ICCD.2003.1240902..

S.C Chan, , , P.J Restle, , , K.L Shepard, , , 等. . A 4.6 GHz resonant global clock distribution network. . 2004. . IEEE Int. Solid-State Circuits Conf. . p.342--343. . DOI:10.1109/ISSCC.2004.1332734http://doi.org/10.1109/ISSCC.2004.1332734..

V.H Cordero, , , S.P Khatri. . Clock distribution scheme using coplanar transmission lines. . 2008. . Design, Automation and Test in Europe. . p.985--990. . DOI:10.1109/DATE.2008.4484809http://doi.org/10.1109/DATE.2008.4484809..

A.J Drake, , , K.J Nowka, , , T.Y Nguyen, , , 等. . Resonant clocking using distributed parasitic capacitance. . IEEE J. Sol.-State Circ., , 2004. . 39((9):):1520--1528. . DOI:10.1109/JSSC.2004.831435http://doi.org/10.1109/JSSC.2004.831435..

A Mandal, , , V Karkala, , , S.P Khatri, , , 等. . Interconnected tile standing wave resonant oscillator based clock distribution circuits. . 2011. . 24th Int. Conf. on VLSI Design. . p.82--87. . DOI:10.1109/VLSID.2011.70http://doi.org/10.1109/VLSID.2011.70..

F O'Mahony. . 10 GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators. . PhD Thesis, Stanford University, USA, , 2003. ..

F O'Mahony, , , C.P Yue, , , M.A Horowitz, , , 等. . A 10-GHz global clock distribution using coupled standing-wave oscillators. . IEEE J. Sol.-State Circ., , 2003. . 38((11):):1813--1820. . DOI:10.1109/JSSC.2003.818299http://doi.org/10.1109/JSSC.2003.818299..

J Wood, , , T.C Edwards, , , S Lipa. . Rotary travelingwave oscillator arrays: a new clock technology. . IEEE J. Sol.-State Circ., , 2001. . 36((11):):1654--1665. . DOI:10.1109/4.962285http://doi.org/10.1109/4.962285..

浏览量

Downloads

CSCD

文章被引用时，请邮件提醒。

Submit

工具集

关联资源

暂无数据