碳纳米管场效应管四进制全加器设计与分析

Mohammad Hossein MOAIYERI; Shima SEDIGHIANI; Fazel SHARIFI; Keivan NAVI

doi:10.1631/FITEE.1500214

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碳纳米管场效应管四进制全加器设计与分析

常规文章 | Updated：2022-05-19

- 碳纳米管场效应管四进制全加器设计与分析
- Design and analysis of carbon nanotube FET based quaternary full adders
- 信息与电子工程前沿（英文） 2016年17卷第10期页码：1056-1066
- Affiliations：
  
  1Faculty of Electrical Engineering, Shahid Beheshti University, Tehran 1983963113, Iran
  2Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, Tehran 1983963113, Iran
- Author bio：
  
  E-mail: h_moaiyeri@sbu.ac.ir
- Funds：
- DOI：10.1631/FITEE.1500214
  中图分类号： TN79
- 收稿：2015-07-07，
  
  录用：2016-9-24，
  
  纸质出版：2016-10
- Accepted：
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碳纳米管场效应管四进制全加器设计与分析[J]. 信息与电子工程前沿（英文）, 2016,17(10):1056-1066.

Mohammad Hossein MOAIYERI, Shima SEDIGHIANI, Fazel SHARIFI, et al. Design and analysis of carbon nanotube FET based quaternary full adders[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(10): 1056-1066.
碳纳米管场效应管四进制全加器设计与分析[J]. 信息与电子工程前沿（英文）, 2016,17(10):1056-1066. DOI： 10.1631/FITEE.1500214.

Mohammad Hossein MOAIYERI, Shima SEDIGHIANI, Fazel SHARIFI, et al. Design and analysis of carbon nanotube FET based quaternary full adders[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(10): 1056-1066. DOI： 10.1631/FITEE.1500214.

摘要

CMOS二进制逻辑受短沟道效应、功率密度及互连约束等条件的限制。非硅多值逻辑计算是克服上述问题的一种有效方案。本研究在碳纳米管场效应管（carbon nanotube field effect transistors

CNTFET）的基础上提出了两种高性能四进制全加单元。该全加单元利用了CNTFET独有的特性，如目标电压阈值可通过调整碳纳米管管径控制、CNTFET具有与p型和n型器件相同的迁移性。通过在Synopsys HSPICE中使用32 nm斯坦福综合CNTFET模型，在多种测试条件下对所述电路单元进行了仿真。与当前水平的四进制全加器相比，本文所采用的设计平均降低延迟32%，所需平均功率、能耗及静态功率分别为现有水平的68%、83%及77%。仿真结果表明，所述设计在生产制程、电压、温度变化、噪声耐受方面具有较好的鲁棒性。

Abstract

CMOS binary logic is limited by short channel effects

power density

and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay

68% average power

83% energy consumption

and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process

voltage

and temperature variations

and are noise tolerant.

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references

S Asif , , , M Vesterbacka . . Performance analysis of radix- 4 adders . . Integr. VLSI J. , , 2012 . . 45 ( ( 2 ): ): 111 - - 120 . . DOI: 10.1016/j.vlsi.2011.09.004 http://doi.org/10.1016/j.vlsi.2011.09.004 . .

G Balamurugan , , , N.R Shanbhag . . The twin-transistor noise-tolerant dynamic circuit technique . . IEEE J. Sol.- State Circ. , , 2001 . . 36 ( ( 2 ): ): 273 - - 280 . . DOI: 10.1109/4.902768 http://doi.org/10.1109/4.902768 . .

Y Chen , , , B Wang , , , P.C.H Poa , , , 等 . . (n, m) selectivity of single-walled carbon nanotubes by different carbon precursors on Co-Mo catalysts . . J. Am. Chem. Soc. , , 2007 . . 129 ( ( 29 ): ): 9014 - - 9019 . . DOI: 10.1021/ja070808k http://doi.org/10.1021/ja070808k . .

Silva, R.C.G da , , , H.I Boudinov , , , L Carro . . A low power high performance CMOS voltage-mode quaternary full adder . . 2006 . . IFIP Int. Conf. on Very Large Scale Integration . . 1130 - - 1133 . . DOI: 10.1109/VLSISOC.2006.313231 http://doi.org/10.1109/VLSISOC.2006.313231 . .

R Datla . . Design and Validation of Quaternary Arithmetic Circuits , , 2009 . . : : USA PhD Thesis, Southern Methodist University , , . .

S.R Datla , , , M.A Thornton , , , L Hendrix , , , 等 . . Quaternary Addition Circuits Based on SUSLOC Voltage- Mode Cells and Modeling with System Verilog? . . 2009 . . 39th IEEE Int. Symp. on Multiple-Valued Logic . . 256 - - 261 . . DOI: 10.1109/ISMVL.2009.66 http://doi.org/10.1109/ISMVL.2009.66 . .

J Deng . . Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors , , 2007 . . : : USA PhD Thesis, Stanford University , , . .

J Deng , , , H.S.P Wong . . A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region . . IEEE Trans. Electron Dev. , , 2007a . . 54 ( ( 12 ): ): 3186 - - 3194 . . DOI: 10.1109/TED.2007.909030 http://doi.org/10.1109/TED.2007.909030 . .

J Deng , , , H.S.P Wong . . A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: full device model and circuit performance benchmarking . . IEEE Trans. Electron Dev. , , 2007b . . 54 ( ( 12 ): ): 3195 - - 3205 . . DOI: 10.1109/TED.2007.909043 http://doi.org/10.1109/TED.2007.909043 . .

E Dubrova . . Multiple-valued logic in VLSI: challenges and opportunities . . 1999 . . Proc. NORCHIP Conf. . . 340 - - 350 . . . .

G Gelao , , , R Marani , , , R Diana , , , 等 . . Semi-empirical SPICE model for n-type conventional CNTFETs . . IEEE Trans. Nanotechnol. , , 2011 . . 10 ( ( 3 ): ): 506 - - 512 . . DOI: 10.1109/TNANO.2010.2049499 http://doi.org/10.1109/TNANO.2010.2049499 . .

S.L Hurst . . Multiple-valued logic—its status and its future . . IEEE Trans. Comput. , , 1984 . . 33 ( ( 12 ): ): 1160 - - 1179 . . DOI: 10.1109/TC.1984.1676392 http://doi.org/10.1109/TC.1984.1676392 . .

Y.B Kim , , , Y.B Kim , , , F Lombardi . . Novel design methodology to optimize the speed and power of the CNTFET circuits . . 2009 . . 52nd IEEE Int. Midwest Symp. on Circuits and Systems . . 1130 - - 1133 . . DOI: 10.1109/MWSCAS.2009.5235967 http://doi.org/10.1109/MWSCAS.2009.5235967 . .

J Liang , , , L Chen , , , J Han , , , 等 . . Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs . . IEEE Trans. Nanotechnol. , , 2014 . . 13 ( ( 4 ): ): 695 - - 708 . . DOI: 10.1109/TNANO.2014.2316000 http://doi.org/10.1109/TNANO.2014.2316000 . .

A Lin , , , N Patil , , , K Ryu , , , 等 . . Threshold voltage and on–off ratio tuning for multiple-tube carbon nanotube FETs . . IEEE Trans. Nanotechnol. , , 2009 . . 8 ( ( 1 ): ): 4 - - 9 . . DOI: 10.1109/TNANO.2008.2004706 http://doi.org/10.1109/TNANO.2008.2004706 . .

S Lin , , , Y.B Kim , , , F Lombardi . . CNTFET-based design of ternary logic gates and arithmetic circuits . . IEEE Trans. Nanotechnol. , , 2011 . . 10 ( ( 2 ): ): 217 - - 225 . . DOI: 10.1109/TNANO.2009.2036845 http://doi.org/10.1109/TNANO.2009.2036845 . .

G.A Mansoori , , , T.F Soelaiman . . Nanotechnology—an introduction for the standards . . J. ASTM Int. , , 2005 . . 2 ( ( 6 ): ): 1 - - 21 . . DOI: 10.1520/JAI13110 http://doi.org/10.1520/JAI13110 . .

R Marani , , , A.G Perri . . A compact, semi-empirical model of carbon nanotube field effect transistors oriented to simulation software . . Current Nanosci. , , 2011 . . 7 ( ( 2 ): ): 245 - - 253 . . DOI: 10.2174/157341311794653613 http://doi.org/10.2174/157341311794653613 . .

R Marani , , , A.G Perri . . A DC model of carbon nanotube field effect transistor for CAD applications . . Int. J. Electron. , , 2012 . . 99 ( ( 3 ): ): 427 - - 444 . . DOI: 10.1080/00207217.2011.629223 http://doi.org/10.1080/00207217.2011.629223 . .

R Marani , , , A.G Perri . . Modelling of CNTFETs for computer aided design of A/D electronic circuits . . Current Nanosci. , , 2014 . . 10 ( ( 3 ): ): 326 - - 333 . . DOI: 10.2174/15734137113096660124 http://doi.org/10.2174/15734137113096660124 . .

R Marani , , , G Gelao , , , A.G Perri . . Modelling of carbon nanotube field effect transistors oriented to SPICE software for A/D circuit design . . Microelectron. J. , , 2013 . . 44 ( ( 1 ): ): 33 - - 39 . . DOI: 10.1016/j.mejo.2011.07.012 http://doi.org/10.1016/j.mejo.2011.07.012 . .

R Marani , , , G Gelao , , , A.G Perri . . Comparison of ABM SPICE library with Verilog-A for compact CNTFET model implementation . . Current Nanosci. , , 2014 . . 8 ( ( 4 ): ): 556 - - 565 . . DOI: 10.2174/157341312801784230 http://doi.org/10.2174/157341312801784230 . .

M.H Moaiyeri , , , A Doostaregan , , , K Navi . . Design of energy-efficient and robust ternary circuits for nanotechnology . . IET Circ. Dev. Syst. , , 2011 . . 5 ( ( 4 ): ): 285 - - 296 . . DOI: 10.1049/iet-cds.2010.0340 http://doi.org/10.1049/iet-cds.2010.0340 . .

M.H Moaiyeri , , , K Navi , , , O Hashemipour . . Design and evaluation of CNFET-based quaternary circuits . . Circ. Syst. Signal Process. , , 2012 . . 31 ( ( 5 ): ): 1631 - - 1652 . . DOI: 10.1007/s00034-012-9413-2 http://doi.org/10.1007/s00034-012-9413-2 . .

K Navi , , , A Doostaregan , , , M.H Moaiyeri , , , 等 . . A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders . . Fuzzy Sets Syst. , , 2011 . . 185 ( ( 1 ): ): 111 - - 124 . . DOI: 10.1016/j.fss.2011.06.006 http://doi.org/10.1016/j.fss.2011.06.006 . .

V Patel , , , K.S Gurumurthy . . Arithmetic operations in multi-valued logic . . Int. J. VLSI Des. Commun. Syst. , , 2010 . . 1 ( ( 1 ): ): 21 - - 32 . . . .

M Pedram , , , X Wu . . A new description of MOS circuits at switch-level with applications . . IEICE Trans. Fundam. Electron. Commun. Comput. Sci. , , 1997 . . 80 ( ( 10 ): ): 1892 - - 1901 . . . .

A Raychowdhury , , , K Roy . . Carbon-nanotube-based voltage-mode multiple-valued logic design . . IEEE Trans. Nanotechnol. , , 2005 . . 4 ( ( 2 ): ): 168 - - 179 . . DOI: 10.1109/TNANO.2004.842068 http://doi.org/10.1109/TNANO.2004.842068 . .

A Raychowdhury , , , K Roy . . Carbon nanotube electronics: design of high-performance and low-power digital circuits . . IEEE Trans. Circ. Systems I , , 2007 . . 54 ( ( 11 ): ): 2391 - - 2401 . . DOI: 10.1109/TCSI.2007.907799 http://doi.org/10.1109/TCSI.2007.907799 . .

F Sharifi , , , M.H Moaiyeri , , , K Navi , , , 等 . . Quaternary full adder cells based on carbon nanotube FETs . . J. Comput. Electron. , , 2015 . . 14 ( ( 3 ): ): 762 - - 772 . . DOI: 10.1007/s10825-015-0714-0 http://doi.org/10.1007/s10825-015-0714-0 . .

I Thoidis , , , D Soudris , , , I Karafyllidis , , , 等 . . Quaternary voltage-mode CMOS circuits for multiple-valued logic . . IEE Proc.-Circ. Dev. Syst. , , 1998 . . 145 ( ( 2 ): ): 71 - - 77 . . DOI: 10.1049/ip-cds:19981763 http://doi.org/10.1049/ip-cds:19981763 . .

X Wu . . Theory of transmission switches and its application to design of CMOS digital circuits . . Int. J. Circ. Theory Appl. , , 1992 . . 20 ( ( 4 ): ): 349 - - 356 . . DOI: 10.1002/cta.4490200402 http://doi.org/10.1002/cta.4490200402 . .

X Wu , , , F Prosser . . Design theory of digital circuits at switch level . . Sci. China Technol. Sci. , , 1996 . . 39 ( ( 4 ): ): 424 - - 434 . . . .

F Yang , , , X Wang , , , D Zhang , , , 等 . . Chirality-specific growth of single-walled carbon nanotubes on solid alloy catalysts . . Nature , , 2014 . . 510 ( ( 7506 ): ): 522 - - 524 . . DOI: 10.1038/nature13434 http://doi.org/10.1038/nature13434 . .

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