一款基于改进的步进式译码算法的流水线架构RS码译码器

Xing-ru PENG; Wei ZHANG; Yan-yan LIU

doi:10.1631/FITEE.1500303

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一款基于改进的步进式译码算法的流水线架构RS码译码器

常规文章 | Updated：2022-05-19

- 一款基于改进的步进式译码算法的流水线架构RS码译码器
- A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm
- 信息与电子工程前沿（英文） 2016年17卷第9期页码：954-961
- Affiliations：
  
  1.School of Electronic and Information Engineering, Tianjin University, Tianjin 300072, China
  2.College of Electronic Information and Optical Engineering, Nankai University, Tianjin 300071, China
- Author bio：
  
  E-mail:tjupengxr@tju.edu.cn
  E-mail:tjuzhangwei@tju.edu.cn
  E-mail:lyytianjin@nankai.edu.cn
- Funds：
  
  Project supported by the National Natural Science Foundation of China (No. 61474080) and the Program for New Century Excellent Talents in University, China
- DOI：10.1631/FITEE.1500303
  中图分类号： TN432
- 收稿：2015-09-20，
  
  录用：2016-2-16，
  
  纸质出版：2016-09
- Accepted：
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一款基于改进的步进式译码算法的流水线架构RS码译码器[J]. 信息与电子工程前沿（英文）, 2016,17(9):954-961.

Xing-ru PENG, Wei ZHANG, Yan-yan LIU. A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 954-961.
一款基于改进的步进式译码算法的流水线架构RS码译码器[J]. 信息与电子工程前沿（英文）, 2016,17(9):954-961. DOI： 10.1631/FITEE.1500303.

Xing-ru PENG, Wei ZHANG, Yan-yan LIU. A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm[J]. Frontiers of Information Technology & Electronic Engineering, 2016, 17(9): 954-961. DOI： 10.1631/FITEE.1500303.

摘要

基于改进的步进式译码算法，我们为超宽带系统设计了一款流水线架构的Reed-Solomon(RS)码译码器。为了减小复杂度，改进的步进式译码算法将传统步进式译码算法中冗余的两部分进行了结合。此外，采用流水线架构，使得所设计的译码器以最小时延获得最大吞吐率。因此，对于RS（23

17）码，我们所设计的译码器面积比ME（modified Euclidean）架构和pDCME（pipelined degree-computationless modified Euclidean）架构分别减少了42.5%和24.4%。此外，与传统步进式译码器相比，我们设计的译码器能减少11.3%的面积，且关键路径延迟更低。

Abstract

We propose a pipelined Reed-Solomon (RS) decoder for an ultra-wideband system using a modified stepby-step algorithm. To reduce the complexity

the modified step-by-step algorithm merges two cases of the original algorithm. The pipelined structure allows the decoder to work at high rates with minimum delay. Consequently

for RS(23

17) codes

the proposed architecture requires 42.5% and 24.4% less area compared with a modified Euclidean architecture and a pipelined degree-computationless modified Euclidean architecture

respectively. The area of the proposed decoder is 11.3% less than that of the previous step-by-step decoder with a lower critical path delay.

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references

JH Baek , , , MH Sunwoo . . New degree computationless modified Euclid algorithm and architecture for Reed-Solomon decoder . . IEEE Trans. VLSI Syst. , , 2006 . . 14 ( ( 8 ): ): 915 - - 920 . . DOI: 10.1109/TVLSI.2006.878484 http://doi.org/10.1109/TVLSI.2006.878484 . .

A Batra , , , J Balakrishnan , , , A Dabak , , , 等 . . Multiband OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a. . . 2004 . . IEEE P802.15-03/268r2 . . . .

ER Berlekamp . . Algebraic Coding Theory . . 1968 . . McGrawHill, New York . . . .

TC Chen , , , MH Tasi . . Hardware implementation of a high-speed (32, 24, 4) RS decoder . . Chung Hua J. Sci. Eng. , , 2007 . . 5 ( ( 4 ): ): 21 - - 27 . . . .

TC Chen , , , CH Wei , , , SW Wei . . Step-by-step decoding algorithm for Reed-Solomon codes . . IEE Proc. Commun. , , 2000 . . 147 ( ( 1 ): ): 8 - - 12 . . DOI: 10.1049/ip-com:20000149 http://doi.org/10.1049/ip-com:20000149 . .

TC Chen , , , CH Wei , , , SW Wei . . A pipeline structure for high-speed step-by-step RS decoding . . IEICE Trans. Commun. , , 2003 . . ( ( E86-B(2) ): ): 847 - - 849 . . . .

AS Das , , , S Das , , , J Bhaumik . . Design of RS(255,251) encoder and decoder in FPGA . . Int. J. Soft Comput. Eng. , , 2013 . . 2 ( ( 6 ): ): 391 - - 394 . . . .

F Garca-Herrero , , , J Valls , , , PK Meher . . High-speed RS(255, 239) decoder based on LCC decoding . . Circ. Syst. Signal Process. , , 2011 . . 30 ( ( 6 ): ): 1643 - - 1669 . . DOI: 10.1007/s00034-011-9327-4 http://doi.org/10.1007/s00034-011-9327-4 . .

W Guo , , , W Gai . . Area-efficient recursive degree computationless modified Euclid’s architecture for ReedSolomon decoder . . 2014 . . Proc. IEEE Int. Conf. on Electron Devices and Solid-State Circuits . . 1 - - 2 . . DOI: 10.1109/EDSSC.2014.7061134 http://doi.org/10.1109/EDSSC.2014.7061134 . .

H Lee . . High-speed VLSI architecture for parallel Reed-Solomon decoder . . IEEE Trans. VLSI Syst. , , 2003 . . 11 ( ( 2 ): ): 288 - - 294 . . DOI: 10.1109/TVLSI.2003.810782 http://doi.org/10.1109/TVLSI.2003.810782 . .

S Lee , , , H Lee . . A high-speed pipelined degreecomputationless modified Euclidean algorithm architecture for Reed-Solomon decoders. IEICE Trans . . Fundament. Electron. Commun. Comput. Sci. , , 2008 . . ( ( E91-A(3) ): ): 830 - - 835 . . . .

X Liu , , , C Lu , , , TH Cheng , , , 等 . . A simplified step-by-step decoding algorithm for parallel decoding of Reed-Solomon codes . . IEEE Trans. Commun. , , 2007 . . 55 ( ( 6 ): ): 1103 - - 1109 . . DOI: 10.1109/TCOMM.2007.898703 http://doi.org/10.1109/TCOMM.2007.898703 . .

J Massey . . Step-by-step decoding of the BoseChaudhuri-Hocquenghem codes . . IEEE Trans. Inform. Theory , , 1965 . . 11 ( ( 4 ): ): 580 - - 585 . . DOI: 10.1109/TIT.1965.1053833 http://doi.org/10.1109/TIT.1965.1053833 . .

DV Sarwate , , , NR Shanbhag . . High-speed architectures for Reed-Solomon decoders . . IEEE Trans. VLSI Syst. , , 2001 . . 9 ( ( 5 ): ): 641 - - 655 . . DOI: 10.1109/92.953498 http://doi.org/10.1109/92.953498 . .

Y Wu . . New scalable decoder architectures for ReedSolomon codes . . IEEE Trans. Commun. , , 2015 . . 63 ( ( 8 ): ): 2741 - - 2761 . . DOI: 10.1109/TCOMM.2015.2445759 http://doi.org/10.1109/TCOMM.2015.2445759 . .

X Zhang , , , J Zhu . . High-throughput interpolation architecture for algebraic soft-decision Reed-Solomon decoding . . IEEE Trans. Circ. Syst. I , , 2010 . . 57 ( ( 3 ): ): 581 - - 591 . . DOI: 10.1109/TCSI.2009.2023935 http://doi.org/10.1109/TCSI.2009.2023935 . .

J Zhu , , , X Zhang , , , Z Wang . . Backward interpolation architecture for algebraic soft-decision Reed-Solomon decoding . . IEEE Trans. VLSI Syst. , , 2009 . . 17 ( ( 11 ): ): 1602 - - 1615 . . DOI: 10.1109/TVLSI.2008.2005575 http://doi.org/10.1109/TVLSI.2008.2005575 . .

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