基于碳纳米管场效应管的新型三元半加器及乘法器

Sepehr Tabrizchi; Nooshin Azimi; Keivan Navi

doi:10.1631/FITEE.1500366

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基于碳纳米管场效应管的新型三元半加器及乘法器

常规文章 | Updated：2022-05-19

- 基于碳纳米管场效应管的新型三元半加器及乘法器
- A novel ternary half adder and multiplier based on carbon nanotube field effect transistors
- 信息与电子工程前沿（英文） 2017年18卷第3期页码：423-433
- Affiliations：
  
  1Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
  2Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, Tehran, Iran
- Author bio：
- Funds：
- DOI：10.1631/FITEE.1500366
  中图分类号： TN4
- 收稿：2015-10-28，
  
  录用：2016-8-10，
  
  纸质出版：2017-03
- Accepted：
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Sepehr Tabrizchi, Nooshin Azimi, Keivan Navi. 基于碳纳米管场效应管的新型三元半加器及乘法器[J]. 信息与电子工程前沿（英文）, 2017,18(3):423-433.

Sepehr TABRIZCHI, Nooshin AZIMI, Keivan NAVI. A novel ternary half adder and multiplier based on carbon nanotube field effect transistors[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(3): 423-433.
Sepehr Tabrizchi, Nooshin Azimi, Keivan Navi. 基于碳纳米管场效应管的新型三元半加器及乘法器[J]. 信息与电子工程前沿（英文）, 2017,18(3):423-433. DOI： 10.1631/FITEE.1500366.

Sepehr TABRIZCHI, Nooshin AZIMI, Keivan NAVI. A novel ternary half adder and multiplier based on carbon nanotube field effect transistors[J]. Frontiers of Information Technology & Electronic Engineering, 2017, 18(3): 423-433. DOI： 10.1631/FITEE.1500366.

摘要

多值逻辑（multiple-valued logic

MVL），例如三元逻辑，在近年来是大量研究项目的研究对象。MVL可以降低必要操作的数目、减小芯片面积。碳纳米管场效应管（CNTFETs）被认为是硅晶体管可行的替代方案。将CNTFETs与MVL结合，可以得到更快、更灵活的独特设计方案。本文利用微纳技术和三元逻辑设计出了新型的半加器和乘法器。微纳技术和三元逻辑的采纳降低了元件功耗和面积，提升了元件运行速度。我们利用斯坦福CNTFET模型和HSPICE软件对本文设计器件进行了仿真，并将仿真结果与相关研究结果进行了对比。

Abstract

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper

we design a new half adder and a new multiplier by nanotechnology using a ternary logic

which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software

and the results are compared with those of other studies.

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