高效节能计算的跨层设计：为实现每瓦特电力每秒千万亿次运算

Xiaobo Sharon HU; Michael NIEMIER

doi:10.1631/FITEE.1800466

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高效节能计算的跨层设计：为实现每瓦特电力每秒千万亿次运算

后E级超算专辑 | Updated：2022-05-19

- 高效节能计算的跨层设计：为实现每瓦特电力每秒千万亿次运算
- Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt
- 信息与电子工程前沿（英文） 2018年19卷第10期页码：1209-1223
- Affiliations：
  
  Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN 46556, USA
- Author bio：
  
  Xiaobo Sharon HU, E-mail: shu@nd.edu
  [ "Michael NIEMIER, E-mail: mniemier@nd.edu" ]
- Funds：
  
  Project supported by the Center for Low Energy Systems Technology (LEAST), one of the six centers of STARnet, a Semiconductor Research Corporation Program sponsored by MARCO and DARPA
- DOI：10.1631/FITEE.1800466
  中图分类号： TP183;TP302
- 收稿：2018-08-05，
  
  修回：2018-10-10，
  
  纸质出版：2018-10
- Accepted：
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Xiaobo Sharon HU, Michael NIEMIER. 高效节能计算的跨层设计：为实现每瓦特电力每秒千万亿次运算[J]. 信息与电子工程前沿（英文）, 2018,19(10):1209-1223.

Xiaobo Sharon HU, Michael NIEMIER. Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(10): 1209-1223.
Xiaobo Sharon HU, Michael NIEMIER. 高效节能计算的跨层设计：为实现每瓦特电力每秒千万亿次运算[J]. 信息与电子工程前沿（英文）, 2018,19(10):1209-1223. DOI： 10.1631/FITEE.1800466.

Xiaobo Sharon HU, Michael NIEMIER. Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt[J]. Frontiers of Information Technology & Electronic Engineering, 2018, 19(10): 1209-1223. DOI： 10.1631/FITEE.1800466.

摘要

由于基于摩尔定律的器件缩小及其性能增长趋势正在放缓，实现快速和高效节能信息处理的新技术和计算模型越来越被关注。与此同时，越来越多证据表明，对于传统布尔电路和冯诺依曼处理器，超CMOS器件很难与CMOS技术竞争。开发利用新兴器件的独特性能，特别是在非传统电路和架构背景下，具有提供在功率、性能和能力方面数十或百、千倍的改进潜力。为充分发挥超CMOS器件的优势，从器件到电路到体系结架再到算法的跨层设计工作不可或缺。在此背景下，本文研究了嵌入式应用中的高性能神经网络加速器，重点阐述了基于非传统器件技术、电路样式到架构的跨层工作的几种深度神经网络加速器的设计，介绍了应用级基准验证研究工作。讨论表明，跨层设计工作的确可以在实现极大规模高效节能处理方面带来数量级的改进。

Abstract

As Moore's law based device scaling and accompanying performance scaling trends are slowing down

there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile

there is growing evidence that

with respect to traditional Boolean circuits and von Neumann processors

it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Exploiting unique characteristics of emerging devices

especially in the context of alternative circuit and architectural paradigms

has the potential to offer orders of magnitude improvement in terms of power

performance

and capability. To take full advantage of beyond-CMOS devices

cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This study examines energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on cross-layer efforts spanning from alternative device technologies

circuit styles

to architectures are highlighted. Application-level benchmarking studies are presented. The discussions demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme-scale energy-efficient processing.

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