基于现场可编程门阵列的不同数据路径架构ANU轻量级密码的设计与实现

Vijay DAHIPHALE; Gaurav BANSOD; Ankur ZAMBARE; Narayan PISHAROTY

doi:10.1631/FITEE.1800681

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基于现场可编程门阵列的不同数据路径架构ANU轻量级密码的设计与实现

常规文章 | Updated：2022-05-19

- 基于现场可编程门阵列的不同数据路径架构ANU轻量级密码的设计与实现
- Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA
- 信息与电子工程前沿（英文） 2020年21卷第4期页码：615-628
- Affiliations：
  
  Pune Institute of Computer Technology, Pune 411043, India
  Iziel Healthcare Pvt. Ltd., Pune 411028, India
- Author bio：
  
  Vijay DAHIPHALE, vijaydahiphale96@gmail.com
  [ "Gaurav BANSOD, E-mail: gaurav249@gmail.com" ]
- Funds：
- DOI：10.1631/FITEE.1800681
  中图分类号： TN918
- 收稿：2018-10-29，
  
  修回：2020-;3-;6，
  
  纸质出版：2020-04
- Accepted：
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Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, 等. 基于现场可编程门阵列的不同数据路径架构ANU轻量级密码的设计与实现[J]. 信息与电子工程前沿（英文）, 2020,21(4):615-628.

DAHIPHALE Vijay, BANSOD Gaurav, ZAMBARE Ankur, et al. Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA[J]. Frontiers of Information Technology & Electronic Engineering, 2020, 21(4): 615-628.
Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, 等. 基于现场可编程门阵列的不同数据路径架构ANU轻量级密码的设计与实现[J]. 信息与电子工程前沿（英文）, 2020,21(4):615-628. DOI： 10.1631/FITEE.1800681.

DAHIPHALE Vijay, BANSOD Gaurav, ZAMBARE Ankur, et al. Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA[J]. Frontiers of Information Technology & Electronic Engineering, 2020, 21(4): 615-628. DOI： 10.1631/FITEE.1800681.

摘要

自物联网（IoT）诞生以来，数据与系统安全一直是开发者关注的重点。由于大多数物联网设备在8位控制器上运行，其容量和计算力有限，因此需要使用轻量级密码在发送端和接收端分别进行加密和解密。提出用于ANU密码硬件实现的新架构，并给出每一架构的相关结果。在相同实施条件下，在4种不同现场可编程门阵列（FPGA）上分别以4位、8位、16位和32位的数据路径尺寸实现ANU密码，并比较每一性能指标。与以往ANU密码架构不同，新架构具有用于高吞吐量和硬件优化的并行替换盒（S盒）。通过不同数据路径设计，在资源极其有限的系统中，ANU密码被证明是实现安全性的最佳选择。

Abstract

Since the dawn of the Internet of Things (IoT)

data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power

encryption and decryption need to be implemented at the transmitting and receiving ends

respectively

using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-

16-

and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition

and the results are compared on every performance metric. Unlike previous ANU architectures

the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs

ANU cipher proves to be the obvious choice for implementing security in extremely resource- constrained systems.

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references

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