一种应用于带有嵌入式存储器的FPGA的BCH纠错方案

刘洋; 李杰; 王瀚; 张德彪; 冯凯强; 李金强

doi:10.1631/FITEE.2000323

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一种应用于带有嵌入式存储器的FPGA的BCH纠错方案

常规文章 | Updated：2022-05-19

- 一种应用于带有嵌入式存储器的FPGA的BCH纠错方案
- A BCH error correction scheme applied to FPGA with embedded memory
- 信息与电子工程前沿（英文） 2021年22卷第8期页码：1127-1139
- Affiliations：
  
  National Key Laboratory for Electronic Measurement Technology, North University of China, Taiyuan 030051, China
  Shandong Aerospace Electronic Technology Institute, Yantai 264000, China
- Author bio：
  
  Yang LIU, E-mail: lylyly357@163.com
  Jie LI, E-mail: lijie@nuc.edu.cn
- Funds：
  
  Project supported by the National Natural Science Foundation of China (No. 61973280) and the China Postdoctoral Science Foundation (No. 2019M661069)
- DOI：10.1631/FITEE.2000323
  中图分类号： TN911
- 收稿：2020-07-05，
  
  修回：2021-;6-;8，
  
  纸质出版：2021-08
- Accepted：
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刘洋, 李杰, 王瀚, 等. 一种应用于带有嵌入式存储器的FPGA的BCH纠错方案[J]. 信息与电子工程前沿（英文）, 2021,22(8):1127-1139.

Yang LIU, Jie LI, Han WANG, et al. A BCH error correction scheme applied to FPGA with embedded memory[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(8): 1127-1139.
刘洋, 李杰, 王瀚, 等. 一种应用于带有嵌入式存储器的FPGA的BCH纠错方案[J]. 信息与电子工程前沿（英文）, 2021,22(8):1127-1139. DOI： 10.1631/FITEE.2000323.

Yang LIU, Jie LI, Han WANG, et al. A BCH error correction scheme applied to FPGA with embedded memory[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(8): 1127-1139. DOI： 10.1631/FITEE.2000323.

摘要

鉴于存储介质上的数据存在位翻转的可能，提出一种模块化的、高速并行的Bose–Chaudhuri–Hocquenghem（BCH）纠错方案，该方案结合了逻辑实现和查找表。所提方案适用于具有片上嵌入式存储器的现场可编程门阵列的数据纠错。详细阐述了系统各部分的优化方法，并分析了该方案在BCH码信息位长度为1024位、码长为1068位且可纠正4位错误情况下的实现过程。

Abstract

Given the potential for bit flipping of data on a memory medium

a high-speed parallel Bose–Chaudhuri–Hocquenghem (BCH) error correction scheme with modular characteristics

combining logic implementation and a look-up table

is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

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references

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