基于电感和变压器跨导提升技术、噪声系数为3.2 dB、带宽为9.8-30.1 GHz的CMOS低噪声放大器

陈宏尘; 朱浩慎; 吴亮; 车文荃; 薛泉

doi:10.1631/FITEE.2000510

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基于电感和变压器跨导提升技术、噪声系数为3.2 dB、带宽为9.8-30.1 GHz的CMOS低噪声放大器

高通量毫米波无线通信专辑 | Updated：2022-05-19

- 基于电感和变压器跨导提升技术、噪声系数为3.2 dB、带宽为9.8-30.1 GHz的CMOS低噪声放大器
  Enhanced Publication
- A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based $ \mathit{\boldsymbol{g_{\rm m}}} $-boosting techniques
- 信息与电子工程前沿（英文） 2021年22卷第4期页码：586-598
- Affiliations：
  
  Guangdong Provincial Key Laboratory of Millimeter-Wave and Terahertz, School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China
  School of Science and Engineering, The Chinese University of Hong Kong, Shenzhen, Shenzhen 518172, China
- Author bio：
  
  [ "Hongchen CHEN, E-mail: hongdoublechen@gmail.com" ]
  [ "Haoshen ZHU, E-mail: zhuhs@scut.edu.cn" ]
  [ "Liang WU, E-mail: wuliang@cuhk.edu.cn" ]
  [ "Wenquan CHE, E-mail: eewqche@scut.edu.cn" ]
  Quan XUE, E-mail: eeqxue@scut.edu.cn
- Funds：
  
  Project supported by the National Key R&D Program of China (No. 2018YFB1802000), the Key-Area R&D Program of Guangdong Province, China (No. 2018B010115001), and the Guangdong Innovative and Entrepreneurial Research Team Program, China (No. 2017ZT07X032)
- DOI：10.1631/FITEE.2000510
  中图分类号： TN92;TN43
- 收稿：2020-09-28，
  
  修回：2021-;2-24，
  
  纸质出版：2021-04
- Accepted：
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陈宏尘, 朱浩慎, 吴亮, 等. 基于电感和变压器跨导提升技术、噪声系数为3.2 dB、带宽为9.8-30.1 GHz的CMOS低噪声放大器[J]. 信息与电子工程前沿（英文）, 2021,22(4):586-598.

Hongchen CHEN, Haoshen ZHU, Liang WU, et al. A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based $ \mathit{\boldsymbol{g_{\rm m}}} $-boosting techniques[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(4): 586-598.
陈宏尘, 朱浩慎, 吴亮, 等. 基于电感和变压器跨导提升技术、噪声系数为3.2 dB、带宽为9.8-30.1 GHz的CMOS低噪声放大器[J]. 信息与电子工程前沿（英文）, 2021,22(4):586-598. DOI： 10.1631/FITEE.2000510.

Hongchen CHEN, Haoshen ZHU, Liang WU, et al. A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based $ \mathit{\boldsymbol{g_{\rm m}}} $-boosting techniques[J]. Frontiers of Information Technology & Electronic Engineering, 2021, 22(4): 586-598. DOI： 10.1631/FITEE.2000510.

摘要

Abstract

A 9.8-30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level

a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level

multiple techniques are proposed to improve LNA performance. First

in the CG stage

loading effect is properly used instead of the conventional feedback technique

to enable simultaneous impedance and noise matching. Second

based on in-depth theoretical analysis

the inductor- and transformer-based

$$g_{\rm m}$$

-boosting techniques are employed for the CG and CS stages

respectively

to enhance the gain and reduce power consumption. Third

the floating-body method

which was originally proposed to lower NF in CS amplifiers

is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology

the LNA chip occupies an area of only 0.2 mm

$$^2$$

and measures a maximum power gain of 10.9 dB with

$$-3$$

dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.

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references

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