
FOLLOWUS
1.Institute of RF-&OE-ICs, Southeast University, Nanjing210096, China
2.Science and Technology on Monolithic Integrated and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing210016, China
3.Engineering Research Center of RF-ICs and RF-Systems, Ministry of Education, Nanjing210096, China
‡Corresponding author
E-mail: zhiqunli@seu.edu.cn
收稿:2020-09-29,
修回:2021-02-19,
网络出版:2022-02-05,
纸质出版:2022-02-0
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黎明, 李智群, 郑权, 等. 17–26.5 GHz 42.5 dBm宽带高效率GaN功率放大器设计[J]. 信息与电子工程前沿(英文), 2022,23(2):346-350.
Ming LI, Zhiqun LI, Quan ZHENG, et al. A 17–26.5 GHz 42.5 dBm broadband and highly efficient gallium nitride power amplifier design[J]. Frontiers of Information Technology & Electronic Engineering, 2022, 23(2): 346-350.
黎明, 李智群, 郑权, 等. 17–26.5 GHz 42.5 dBm宽带高效率GaN功率放大器设计[J]. 信息与电子工程前沿(英文), 2022,23(2):346-350. DOI: 10.1631/FITEE.2000513.
Ming LI, Zhiqun LI, Quan ZHENG, et al. A 17–26.5 GHz 42.5 dBm broadband and highly efficient gallium nitride power amplifier design[J]. Frontiers of Information Technology & Electronic Engineering, 2022, 23(2): 346-350. DOI: 10.1631/FITEE.2000513.
提出一种在微波频段具有宽带、高效率的氮化镓(GaN)功率放大器。该功率放大器采用0.15 μm栅长GaN-HEMT工艺,其工作频段可以覆盖整个K频段,即17–26.5 GHz。为获得更好的输出功率和功率附加效率(PAE),根据晶体管的性能,设计了最优前后级驱动比和最佳晶体管尺寸,并采用宽带低损耗电路拓扑结构,实现宽带高效率设计。同时,将谐波控制结构巧妙地集成到驱动级匹配电路中,提升高频效率,确保整个频段内获得较高功率附加效率。该功率放大器采用三级放大拓扑结构,在连续波条件下,测试结果表明,在17–26.5 GHz频带范围内饱和输出功率超过42.5 dBm,平均PAE为30%,在19.8 GHz时PAE达到最大,为32.1%,输出功率平坦度优于1.0 dB。该芯片结构紧凑,面积仅为4.2 mm×3.0 mm,可广泛应用于收发组件、无线通信、电子测量仪器等领域。
A gallium nitride (GaN) power amplifier monolithic microwave integrated circuit (MMIC) with a wide band and high efficiency in the microwave frequency band is proposed in this study. The power amplifier MMIC uses a 0.15 μm GaN high electron mobility transistor (HEMT) process. The operating frequency band of the amplifier can cover the whole K-band
i.e.
17–26.5 GHz. To obtain better output power and power added efficiency (PAE)
the power amplifier MMIC is designed with the optimal driving ratio of the front and rear stages and the optimal size of the transistor according to the performance of the transistor
and a broadband low-loss circuit topology is adopted to realize the broadband high-efficiency design. The harmonic control structure is integrated into the drive-stage matching circuit to improve the high-frequency efficiency and keep the PAE high performance in the whole frequency band. In the continuous wave (CW) mode
results show that the power amplifier
using a three-stage topology
demonstrates over 42.5 dBm saturated output power in the frequency range of 17–26.5 GHz
an average PAE of 30%
and the maximum value of PAE is 32.1% at 19.8 GHz. The output power flatness is better than 1.0 dB. The chip has a compact structure and an area of 4.2 mm×3.0 mm
and can be widely used in transceiver components
wireless communications
electronic measuring instruments
etc.
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