基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器

Ayoub SADEGHI; Razieh GHASEMI; Hossein GHASEMIAN; Nabiollah SHIRI

doi:10.1631/FITEE.2200077

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基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器

常规文章 | Updated：2023-05-08

- 基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器
- Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits
- 信息与电子工程前沿(英文版) 2023年24卷第4期页码：599-616
- Affiliations：
  
  1.Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz 7198774731, Iran
  2.School of Electrical Engineering, Iran University of Science and Technology, Tehran 1684613114, Iran
  3.Department of Electrical and Electronic Engineering, Shiraz University of Technology, Shiraz 7155713876, Iran
- Author bio：
  
  ‡ Corresponding author
- Funds：
- DOI：10.1631/FITEE.2200077
  中图分类号： TN43
- 收稿：2022-03-01，
  
  修回：2022-09-13，
  
  纸质出版：2023-04-0
- Accepted：
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Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, 等. 基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器[J]. 信息与电子工程前沿(英文版), 2023,24(4):599-616.

Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, et al. Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(4): 599-616.
Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, 等. 基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器[J]. 信息与电子工程前沿(英文版), 2023,24(4):599-616. DOI： 10.1631/FITEE.2200077.

Ayoub SADEGHI, Razieh GHASEMI, Hossein GHASEMIAN, et al. Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(4): 599-616. DOI： 10.1631/FITEE.2200077.

摘要

碳纳米管场效应晶体管（CNTFET）可替代传统晶体管，尤其在基于近似计算的容错数字电路中。本文结合CNTFET技术和栅极扩散输入（GDI）技术，提出3种分别具有6、6和8个晶体管的基于近似计算的全加器。采用基于非支配排序的遗传算法II，将管数和手性向量作为变量，对所提单元进行性能寻优。结果表明，在电路面积有所增加的情况下，功耗延时积性能指标提升约50%。采用蒙特卡罗方法（MCM）和32 nm CNTFET技术，评估所提电路在制造过程中的工艺偏差和稳定性。与文献中的方法相比，所提电路具有更高稳定性。在电路晶体管中使用的动态阈值技术修正了可能出现的输出压降。所提电路出色的电路性能和差错率使其可以作为复杂算术电路（如乘法器）的最低有效位（LSB）部分。

Abstract

Carbon nanotube field-effect transistors (CNTFETs) are reliable alternatives for conventional transistors

especially for use in approximate computing (AC) based error-resilient digital circuits. In this paper

CNTFET technology and the gate diffusion input (GDI) technique are merged

and three new AC-based full adders (FAs) are presented with 6

and 8 transistors

separately. The nondominated sorting based genetic algorithm II (NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits’ improvement by about 50% in terms of power-delay-product (PDP) at the cost of area occupation. The Monte Carlo method (MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process

in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold (DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit (LSB) parts of more complex arithmetic circuits such as multipliers.

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references

Abdul Hadi MF , Hussin H , Soin N , 2022 . The impact of variation in diameter and dielectric materials of the CNT field-effect transistor . ECS J Sol State Sci Technol , 11 ( 2 ): 023002 . https://doi.org/10.1149/2162-8777/ac4ffc https://doi.org/10.1149/2162-8777/ac4ffc

Abiri E , Darabi A , Salehi MR , et al. , 2020 . Optimized gate diffusion input method-based reversible magnitude arithmetic unit using non-dominated sorting genetic algorithm II . Circ Syst Signal Process , 39 ( 9 ): 4516 - 4551 . https://doi.org/10.1007/s00034-020-01382-1 https://doi.org/10.1007/s00034-020-01382-1

Ben-Jamaa MH , Mohanram K , de Micheli G , 2011 . An efficient gate library for ambipolar CNTFET logic . IEEE Trans Comput-Aided Des Integr Circ Syst , 30 ( 2 ): 242 - 255 . https://doi.org/10.1109/tcad.2010.2085250 https://doi.org/10.1109/tcad.2010.2085250

Cardenas JA , Lu SH , Williams NX , et al. , 2021 . In-place printing of flexible electrolyte-gated carbon nanotube transistors with enhanced stability . IEEE Electron Dev Lett , 42 ( 3 ): 367 - 370 . https://doi.org/10.1109/led.2021.3055787 https://doi.org/10.1109/led.2021.3055787

Cho G , Lombardi F , 2016 . Design and process variation analysis of CNTFET-based ternary memory cells . Integration , 54 : 97 - 108 . https://doi.org/10.1016/j.vlsi.2016.02.003 https://doi.org/10.1016/j.vlsi.2016.02.003

Deb K , Pratap A , Agarwal S , et al. , 2002 . A fast and elitist multiobjective genetic algorithm: NSGA-II . IEEE Trans Evol Comput , 6 ( 2 ): 182 - 197 . https://doi.org/10.1109/4235.996017 https://doi.org/10.1109/4235.996017

Deng J , Wong HSP , 2007a . A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region . IEEE Trans Electron Dev , 54 ( 12 ):‍ 3186 - 3194 . https://doi.org/10.1109/ted.2007.909030 https://doi.org/10.1109/ted.2007.909030

Deng J , Wong HSP , 2007b . A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: full device model and circuit performance benchmarking . IEEE Trans Electron Dev , 54 ( 12 ): 3195 - 3205 . https://doi.org/10.1109/ted.2007.909043 https://doi.org/10.1109/ted.2007.909043

Ghasemian A , Abiri E , Hassanli K , et al. , 2022 . HF-QSRAM: half-select free quaternary SRAM design with required peripheral circuits for IoT/IoVT applications . ECS J Sol State Sci Technol , 11 ( 1 ): 011002 . https://doi.org/10.1149/2162-8777/ac4798 https://doi.org/10.1149/2162-8777/ac4798

Ghorbani A , Dolatshahi M , Zanjani SM , et al. , 2022 . A new low-power dynamic-GDI full adder in CNFET technology . Integration , 83 : 46 - 59 . https://doi.org/10.1016/j.vlsi.2021.12.001 https://doi.org/10.1016/j.vlsi.2021.12.001

Gupta V , Mohapatra D , Raghunathan A , et al. , 2013 . Low-power digital signal processing using approximate adders . IEEE Trans Comput-Aided Des Integr Circ Syst , 32 ( 1 ): 124 - 137 . https://doi.org/10.1109/tcad.2012.2217962 https://doi.org/10.1109/tcad.2012.2217962

Hasan M , Zaman HU , Hossain M , et al. , 2020 . Gate diffusion input technique based full swing and scalable 1-bit hybrid full adder for high performance applications . Eng Sci Technol Int J , 23 ( 6 ): 1364 - 1373 . https://doi.org/10.1016/j.jestch.2020.05.008 https://doi.org/10.1016/j.jestch.2020.05.008

Homulle H , Song L , Charbon E , et al. , 2018 . The cryogenic temperature behavior of bipolar, MOS, and DTMOS transistors in standard CMOS . IEEE J Electron Dev Soc , 6 : 263 - 270 . https://doi.org/10.1109/jeds.2018.2798281 https://doi.org/10.1109/jeds.2018.2798281

Huang JL , Zhu MH , Gupta P , et al. , 2010 . A CAD tool for design and analysis of CNFET circuits . Proc IEEE Int Conf of Electron Devices and Solid-State Circuits , p. 1 - 4 . https://doi.org/10.1109/edssc.2010.5713735 https://doi.org/10.1109/edssc.2010.5713735

Huang JL , Zhu MH , Yang SQ , et al. , 2012 . A physical design tool for carbon nanotube field-effect transistor circuits . ACM J Emerg Technol Comput Syst , 8 ( 3 ): 25 . https://doi.org/10.1145/2287696.2287708 https://doi.org/10.1145/2287696.2287708

Huang JQ , Kumar TN , Almurib HAF , et al. , 2021 . Commutative approximate adders: analysis and evaluation . Proc IEEE/ACM Int Symp on Nanoscale Architectures , p. 1 - 6 . https://doi.org/10.1109/nanoarch53687.2021.9642233 https://doi.org/10.1109/nanoarch53687.2021.9642233

Kandpal J , Tomar A , Agarwal M , et al. , 2020 . High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell . IEEE Trans Very Large Scale Integr Syst , 28 ( 6 ): 1413 - 1422 . https://doi.org/10.1109/tvlsi.2020.2983850 https://doi.org/10.1109/tvlsi.2020.2983850

Karimi A , Rezai A , 2016 . Improved device performance in CNTFET using genetic algorithm . ECS J Sol State Sci Technol , 6 ( 1 ): M9 - M12 . https://doi.org/10.1149/2.0101701jss https://doi.org/10.1149/2.0101701jss

Karimi A , Rezai A , 2017 . A design methodology to optimize the device performance in CNTFET . ECS J Sol State Sci Technol , 6 ( 8 ): M97 - M102 . https://doi.org/10.1149/2.0181708jss https://doi.org/10.1149/2.0181708jss

Kordrostami Z , Raeini AGN , Ghoddus H , 2019 . Design and optimization of lightly doped CNTFET architectures based on NEGF method and PSO algorithm . ECS J Sol State Sci Technol , 8 ( 4 ): M39 - M44 . https://doi.org/10.1149/2.0121904jss https://doi.org/10.1149/2.0121904jss

Lee C , Wong HSP , 2015 . Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model 1.0.1 . NanoHUB . https://nanohub.org/publications/42/2 https://nanohub.org/publications/42/2 [ Accessed on Mar. 1, 2022 ].

Lindert N , Sugii T , Tang S , et al. , 1999 . Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages . IEEE J Sol-State Circ , 34 ( 1 ): 85 - 89 . https://doi.org/10.1109/4.736659 https://doi.org/10.1109/4.736659

Mahdiani HR , Ahmadi A , Fakhraie SM , et al. , 2010 . Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications . IEEE Trans Circ Syst I Regul Papers , 57 ( 4 ): 850 - 862 . https://doi.org/10.1109/tcsi.2009.2027626 https://doi.org/10.1109/tcsi.2009.2027626

Majerus S , Merrill W , Garverick SL , 2013 . Design and long-term operation of high-temperature, bulk-CMOS integrated circuits for instrumentation and control . Proc IEEE Energytech , p. 1 - 6 . https://doi.org/10.1109/energytech.2013.6645305 https://doi.org/10.1109/energytech.2013.6645305

Mirzaei M , Mohammadi S , 2020 . Process variation-aware approximate full adders for imprecision-tolerant applications . Comput Electr Eng , 87 : 106761 . https://doi.org/10.1016/j.compeleceng.2020.106761 https://doi.org/10.1016/j.compeleceng.2020.106761

Mirzaei M , Mohammadi S , 2021 . Low-power and variation-aware approximate arithmetic units for image processing applications . AEU Int J Electron Commun , 138 : 153825 . https://doi.org/10.1016/j.aeue.2021.153825 https://doi.org/10.1016/j.aeue.2021.153825

Morgenshtein A , Fish A , Wagner I , 2002 . Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits . IEEE Trans Very Large Scale Integr Syst , 10 ( 5 ): 566 - 581 . https://doi.org/10.1109/tvlsi.2002.801578 https://doi.org/10.1109/tvlsi.2002.801578

Morgenshtein A , Yuzhaninov V , Kovshilovsky A , et al. , 2014 . Full-swing gate diffusion input logic—case-study of low-power CLA adder design . Integration , 47 ( 1 ): 62 - 70 . https://doi.org/10.1016/j.vlsi.2013.04.002 https://doi.org/10.1016/j.vlsi.2013.04.002

Naseri H , Timarchi S , 2018 . Low-power and fast full adder by exploring new XOR and XNOR gates . IEEE Trans Very Large Scale Integr Syst , 26 ( 8 ): 1481 - 1493 . https://doi.org/10.1109/tvlsi.2018.2820999 https://doi.org/10.1109/tvlsi.2018.2820999

Rafiee M , Sadeghi Y , Shiri N , et al. , 2021a . An approximate CNTFET 4:‍2 compressor based on gate diffusion input and dynamic threshold . Electron Lett , 57 ( 17 ): 650 - 652 . https://doi.org/10.1049/ell2.12221 https://doi.org/10.1049/ell2.12221

Rafiee M , Pesaran F , Sadeghi A , et al. , 2021b . An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications . Microelectron J , 118 : 105287 . https://doi.org/10.1016/j.mejo.2021.105287 https://doi.org/10.1016/j.mejo.2021.105287

Rafiee M , Shiri N , Sadeghi A , 2022a . High-performance 1-bit full adder with excellent driving capability for multistage structures . IEEE Embed Syst Lett , 14 ( 1 ): 47 - 50 . https://doi.org/10.1109/les.2021.3108474 https://doi.org/10.1109/les.2021.3108474

Sabetzadeh F , Moaiyeri MH , Ahmadinejad M , 2019 . A majority-based imprecise multiplier for ultra-efficient approximate image multiplication . IEEE Trans Circ Syst I Regul Papers , 66 ( 11 ): 4200 - 4208 . https://doi.org/10.1109/tcsi.2019.2918241 https://doi.org/10.1109/tcsi.2019.2918241

Sadeghi A , Shiri N , Rafiee M , 2020 . High-efficient, ultra-low-power and high-speed 4:2 compressor with a new full adder cell for bioelectronics applications . Circ Syst Signal Process , 39 ( 12 ): 6247 - 6275 . https://doi.org/10.1007/s00034-020-01459-x https://doi.org/10.1007/s00034-020-01459-x

Sadeghi A , Shiri N , Rafiee M , et al. , 2022 . An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending . Front Inform Technol Electron Eng , 23 ( 6 ): 950 - 965 . https://doi.org/10.1631/FITEE.2100432 https://doi.org/10.1631/FITEE.2100432

Strollo AGM , Napoli E , de Caro D , et al. , 2020 . Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers . IEEE Trans Circ Syst I Regul Papers , 67 ( 9 ): 3021 - 3034 . https://doi.org/10.1109/tcsi.2020.2988353 https://doi.org/10.1109/tcsi.2020.2988353

Vasantha Kumar BVP , Murthy Sharma NS , Lal Kishore K , 2012 . A technique to reduce glitch power during physical design stage for low power and less IR drop . Int J Comput Appl , 39 ( 18 ): 62 - 67 . https://doi.org/10.5120/5086-7450 https://doi.org/10.5120/5086-7450

Venkatachalam S , Ko SB , 2017 . Design of power and area efficient approximate multipliers . IEEE Trans Very Large Scale Integr Syst , 25 ( 5 ): 1782 - 1786 . https://doi.org/10.1109/tvlsi.2016.2643639 https://doi.org/10.1109/tvlsi.2016.2643639

Waris H , Wang CH , Liu WQ , 2019 . High-performance approximate half and full adder cells using NAND logic gate . IEICE Electron Expr , 16 ( 6 ): 20190043 . https://doi.org/10.1587/elex.16.20190043 https://doi.org/10.1587/elex.16.20190043

Waris H , Wang CH , Liu WQ , et al. , 2022 . Hybrid partial product-based high-performance approximate recursive multipliers . IEEE Trans Emerg Top Comput , 10 ( 1 ): 507 - 513 . https://doi.org/10.1109/tetc.2020.3013977 https://doi.org/10.1109/tetc.2020.3013977

Yang ZX , Han J , Lombardi F , 2015 . Transmission gate-based approximate adders for inexact computing . Proc IEEE/ACM Int Symp on Nanoscale Architectures , p. 145 - 150 . https://doi.org/10.1109/nanoarch.2015.7180603 https://doi.org/10.1109/nanoarch.2015.7180603

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