基于量子点元胞自动机的低能耗、高速度和高效面积时序电路：T型锁存器和计数器研究

Mohammad GHOLAMI; Zaman AMIRZADEH

doi:10.1631/FITEE.2200361

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基于量子点元胞自动机的低能耗、高速度和高效面积时序电路：T型锁存器和计数器研究

常规文章 | Updated：2023-03-24

- 基于量子点元胞自动机的低能耗、高速度和高效面积时序电路：T型锁存器和计数器研究
- Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study
- 信息与电子工程前沿(英文版) 2023年24卷第3期页码：457-469
- Affiliations：
  
  1.Department of Electrical Engineering, Faculty of Engineering and Technology, University of Mazandaran, Babolsar 4741613534, Iran
  2.Department of Electrical Engineering, Mazandaran University of Science and Technology, Babol 4716685635, Iran
- Author bio：
  
  ‡Corresponding author
- Funds：
  
  the Iran National Science Foundation(4005782)
- DOI：10.1631/FITEE.2200361
  中图分类号： TN79
- 收稿：2022-08-28，
  
  修回：2022-11-22，
  
  纸质出版：2023-03-0
- Accepted：
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Mohammad GHOLAMI, Zaman AMIRZADEH. 基于量子点元胞自动机的低能耗、高速度和高效面积时序电路：T型锁存器和计数器研究[J]. 信息与电子工程前沿(英文版), 2023,24(3):457-469.

Mohammad GHOLAMI, Zaman AMIRZADEH. Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(3): 457-469.
Mohammad GHOLAMI, Zaman AMIRZADEH. 基于量子点元胞自动机的低能耗、高速度和高效面积时序电路：T型锁存器和计数器研究[J]. 信息与电子工程前沿(英文版), 2023,24(3):457-469. DOI： 10.1631/FITEE.2200361.

Mohammad GHOLAMI, Zaman AMIRZADEH. Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study[J]. Frontiers of Information Technology & Electronic Engineering, 2023, 24(3): 457-469. DOI： 10.1631/FITEE.2200361.

摘要

量子点元胞自动机（QCA）是一种用于实现纳米数字电路的新型纳米技术。这种纳米技术在速度、面积和功耗方面都优于互补金属氧化物半导体（CMOS）技术，并且可以显著改善各种逻辑电路设计。本文提出一种在QCA技术中实现T型锁存器的新方法，该方法利用了QCA在时序和时钟相位上的固有特征，因此，所提单元结构与现有方法相比占用面积更少，功耗更低。与之前的最佳设计相比，该T型锁存器的占用面积减少6.45%，功耗降低44.49%。此外，本文首次设计了基于复位的T型锁存器和具有置位和复位功能的T型锁存器。基于所提T型锁存器，开发了一种新型3位计数器，与之前的最佳设计相比减少2.14%的单元数。在3位计数器的基础上，设计了4位计数器，与之前的设计相比，减少0.51%的单元数和4.16%的截面积。此外还引入两个选择性计数器，分别从0到5和从2到5进行计数。在相干矢量引擎模式下，使用QCADesigner和QCAPro软件进行模拟，并将所提电路与相关设计在延迟、单元数、面积和漏电功率方面进行了比较。

Abstract

Quantum-dot cellular automata (QCA) is a new nanotechnology for the implementation of nano-sized digital circuits. This nanotechnology is remarkable in terms of speed

area

and power consumption compared to complementary metal-oxide-semiconductor (CMOS) technology and can significantly improve the design of various logic circuits. We propose a new method for implementing a T-latch in QCA technology in this paper. The proposed method uses the intrinsic features of QCA in timing and clock phases

and therefore

the proposed cell structure is less occupied and less power-consuming than existing implementation methods. In the proposed T-latch

compared to previous best designs

reductions of 6.45% in area occupation and 44.49% in power consumption were achieved. In addition

for the first time

a reset-based T-latch and a T-latch with set and reset capabilities are designed. Using the proposed T-latch

a new 3-bit counter is developed which reduces 2.14% cell numbers compared to the best of previous designs. Moreover

based on the 3-bit counter

a 4-bit counter is designed

which reduces 0.51% cell numbers and 4.16% cross-section area compared to previous designs. In addition

two selective counters are introduced to count from 0 to 5 and from 2 to 5. Simulations were performed using QCADesigner and QCAPro tools in coherence vector engine mode. The proposed circuits are compared with related designs in terms of delay

cell numbers

area

and leakage power.

关键词

Keywords

references

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