自动原理图生成技术综述及其在印刷电路板中的应用

杨杰; 乔凯; 陈健; 陈辰; 郭利翔; 闫镔

doi:10.1631/FITEE.2400612

Your Location：

Home >

Browse articles >

自动原理图生成技术综述及其在印刷电路板中的应用

常规文章 | Updated：2025-11-05

- 自动原理图生成技术综述及其在印刷电路板中的应用
- A review of automatic schematic generation techniques and their application to printed circuit boards
- 信息与电子工程前沿（英文） 2025年26卷第9期页码：1534-1550
- Affiliations：
  
  Information Engineering University, Zhengzhou 450000, China
- Author bio：
  
  E-mail: evil126126@126.com
  qiaokai1992@gmail.com
  ‡ Corresponding author
- Funds：
  
  Laboratory for Advanced Computing and Intelligence Engineering, China
- DOI：10.1631/FITEE.2400612
  中图分类号： TP391.7
- 收稿：2024-07-21，
  
  修回：2025-03-25，
  
  纸质出版：2025-09
- Accepted：
Scan QR Code
杨杰, 乔凯, 陈健, 等. 自动原理图生成技术综述及其在印刷电路板中的应用[J]. 信息与电子工程前沿（英文）, 2025,26(9):1534-1550.

Jie YANG, Kai QIAO, Jian CHEN, et al. A review of automatic schematic generation techniques and their application to printed circuit boards[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1534-1550.
杨杰, 乔凯, 陈健, 等. 自动原理图生成技术综述及其在印刷电路板中的应用[J]. 信息与电子工程前沿（英文）, 2025,26(9):1534-1550. DOI： 10.1631/FITEE.2400612.

Jie YANG, Kai QIAO, Jian CHEN, et al. A review of automatic schematic generation techniques and their application to printed circuit boards[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1534-1550. DOI： 10.1631/FITEE.2400612.

摘要

印刷电路板（PCB）是电子设备的基石，其原理图对系统性能与可靠性具有至关重要的影响。随着电子设备在社会中的广泛应用，其维护、安全、后门以及其他潜在问题备受关注。自动原理图生成（ASG）凭借其自主生成电路原理图的独特能力，不仅在电子设计自动化（EDA）中扮演着举足轻重的角色，更能助力解析PCB设备的基本原理，从而有效应对这些深层问题。然而，受制于PCB日趋精密化的制造工艺以及逆向工程固有的法律和伦理争议，相关技术发展面临显著瓶颈。为突破技术壁垒，推动技术进步，本文系统梳理现有ASG技术，深入剖析其核心算法——布局与布线技术，并针对该技术在PCB逆向工程中的应用，详细分析当前面临的挑战和难题。围绕这些挑战，本文探讨了可行解决方案，旨在推动自动PCB原理图生成技术的研究，为EDA和PCB逆向工程自动化贡献新的力量。

Abstract

The printed circuit board (PCB) stands as the cornerstone of electronic equipment

with its schematic holding paramount importance for system performance and reliability. In light of the pervasive use of electronic devices in society

concerns regarding maintenance

safety

backdoors

and other latent issues have garnered significant attention. Automatic schematic generation (ASG)

with its distinct capability for generating circuit schematics autonomously

not only plays a pivotal role in electronic design automation (EDA) but also aids in deciphering the fundamental principles of PCB equipment to effectively address these underlying issues. However

constrained by the increasingly sophisticated manufacturing processes of PCBs and the inherent legal and ethical controversies surrounding reverse engineering

the development of related technologies faces notable bottlenecks. To break through technical barriers and advance technological progress

this paper comprehensively combs through the existing ASG

offers in-depth description of the core algorithms of the technology—layout and routing

and for the application of the technology in PCB reverse engineering

analyzes in detail the current challenges and the faced problems. Around these challenges

feasible solutions are discussed in this paper

with the aims of promoting the research of automatic PCB schematic generation technology and contributing new strength to EDA and PCB reverse engineering automation.

关键词

Keywords

references

Abel LC , 1972 . On the ordering of connections for automatic wire routing . IEEE Trans Comput , C-21 ( 11 ): 1227 - 1233 . https://doi.org/10.1109/T-C.1972.223482 https://doi.org/10.1109/T-C.1972.223482

Agnesina A , Chang K , Lim SK , 2020 . VLSI placement parameter optimization using deep reinforcement learning . Proc IEEE/ACM Int Conf on Computer-Aided Design , p. 1 - 9 .

Arsintescu BG , 1996 . A method for analog circuits visualization . Proc Int Conf on Computer Design. VLSI in Computers and Processors , p. 454 - 459 . https://doi.org/10.1109/ICCD.1996.563593 https://doi.org/10.1109/ICCD.1996.563593

Botero UJ , Wilson R , Lu HW , et al. , 2020 . Hardware trust and assurance through reverse engineering: a survey and outlook from image analysis and machine learning perspectives . https://doi.org/10.48550/arXiv.2002.04210 https://doi.org/10.48550/arXiv.2002.04210

Cheng RY , Yan JC , 2021 . On joint learning for solving placement and routing in chip design . Proc 35 th Int Conf on Neural Information Processing Systems , Article 1262 .

Chu C , Wong YC , 2008 . FLUTE: fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design . IEEE Trans Computer-Aided Des Integr Circ Syst , 27 ( 1 ): 70 - 83 . https://doi.org/10.1109/TCAD.2007.907068 https://doi.org/10.1109/TCAD.2007.907068

Du XB , Wang CH , Zhong RZ , et al. , 2023 . HubRouter: learning global routing via hub generation and pin-hub connection . Proc 37 th Int Conf on Neural Information Processing Systems , Article 3435 .

Frezza ST , Levitan SP , 1993 . SPAR: a schematic place and route system . IEEE Trans Computer-Aided Des Integr Circ Syst , 12 ( 7 ): 956 - 973 . https://doi.org/10.1109/43.238032 https://doi.org/10.1109/43.238032

Fu RL , Zhang ZM , Tang GM , et al. , 2020 . Design automation methodology from RTL to gate-level netlist and schematic for RSFQ logic circuits . Proc Great Lakes Symp on VLSI , p. 145 - 150 . https://doi.org/10.1145/3386263.3406898 https://doi.org/10.1145/3386263.3406898

Garg B , Agrawal A , Sehgal R , et al. , 2008 . Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist . Proc IEEE East-West Design & Test Symp , p. 379 - 382 . https://doi.org/10.1109/EWDTS.2008.5580148 https://doi.org/10.1109/EWDTS.2008.5580148

Goldie A , Mirhoseini A , 2020 . Placement optimization with deep reinforcement learning . Proc Int Symp on Physical Design , p. 3 - 7 . https://doi.org/10.1145/3372780.3378174 https://doi.org/10.1145/3372780.3378174

Hanan M , 1966 . On Steiner’s problem with rectilinear distance . SIAM J Appl Math , 14 ( 2 ): 255 - 265 . https://doi.org/10.1137/0114025 https://doi.org/10.1137/0114025

Hart PE , Nilsson NJ , Raphael B , 1968 . A formal basis for the heuristic determination of minimum cost paths . IEEE Trans Syst Sci Cybern , 4 ( 2 ): 100 - 107 . https://doi.org/10.1109/TSSC.1968.300136 https://doi.org/10.1109/TSSC.1968.300136

Hong XN , Lin T , Shi YQ , et al. , 2023 . GraphClusNet: a hierarchical graph neural network for recovered circuit netlist partitioning . IEEE Trans Artif Intell , 4 ( 5 ): 1199 - 1213 . https://doi.org/10.1109/TAI.2022.3198930 https://doi.org/10.1109/TAI.2022.3198930

Hsu HY , Lin MPH , 2022 . Automatic analog schematic diagram generation based on building block classification and reinforcement learning . Proc ACM/IEEE 4 th Workshop on Machine Learning for CAD , p. 43 - 48 . https://doi.org/10.1109/MLCAD55463.2022.9900093 https://doi.org/10.1109/MLCAD55463.2022.9900093

Jehng YS , Chen LG , Parng TM , 1991 . ASG: automatic schematic generator . Integration , 11 ( 1 ): 11 - 27 . https://doi.org/10.1016/0167-9260(91)90004-5 https://doi.org/10.1016/0167-9260(91)90004-5

Jumper J , Evans R , Pritzel A , et al. , 2021 . Highly accurate protein structure prediction with AlphaFold . Nature , 596 ( 7873 ): 583 - 589 . https://doi.org/10.1038/s41586-021-03819-2 https://doi.org/10.1038/s41586-021-03819-2

Kastner R , Bozorgzadeh E , Sarrafzadeh M , 2000 . Predictable routing . IEEE/ACM Int Conf on Computer-Aided Design , p. 110 - 113 . https://doi.org/10.1109/ICCAD.2000.896459 https://doi.org/10.1109/ICCAD.2000.896459

Katsuki K , Shin D , Onizawa N , et al. , 2022 . Fast solving complete 2000-node optimization using stochastic-computing simulated annealing . 29 th IEEE Int Conf on Electronics, Circuits and Systems , p. 1 - 4 . https://doi.org/10.1109/ICECS202256217.2022.9971124 https://doi.org/10.1109/ICECS202256217.2022.9971124

Kim NH , Kim KS , Choi KM , et al. , 2000 . RightTopologizer: an efficient schematic generator for multi-level optimization . Proc 13 th Annual IEEE Int ASIC/SOC Conf , p. 387 - 391 . https://doi.org/10.1109/ASIC.2000.880769 https://doi.org/10.1109/ASIC.2000.880769

Lageweg CR , 1998 . Designing an Automatic Schematic Generator for a Netlist Description. Technical Report No. 1-68340-44(1998)03 , Laboratory of Computer Architecture and Digital Techniques, Delft University of Technology , Delft, the Netherlands .

Lai Y , Liu JX , Tang ZT , et al. , 2023 . ChiPFormer: transferable chip placement via offline decision transformer . Proc 40 th Int Conf on Machine Learning , Article 757 .

Lee TD , McNamee LP , 1989 . Structure optimization in logic schematic generation . IEEE Int Conf on Computer-Aided Design Digest of Technical Papers , p. 330 - 333 . https://doi.org/10.1109/ICCAD.1989.76964 https://doi.org/10.1109/ICCAD.1989.76964

Lee TD , McNamee LP , 1992 . Aesthetic routing for transistor schematics . IEEE/ACM Int Conf on Computer-Aided Design , p. 35 - 38 . https://doi.org/10.1109/ICCAD.1992.279400 https://doi.org/10.1109/ICCAD.1992.279400

Liao HG , Zhang WT , Dong XL , et al. , 2020 . A deep reinforcement learning approach for global routing . J Mech Des , 142 ( 6 ): 061701 . https://doi.org/10.1115/1.4045044 https://doi.org/10.1115/1.4045044

Mata RC , Azmib S , Daudc R , et al. , 2006 . Reverse engineering for obsolete single layer printed circuit board (PCB) . Int Conf on Computing & Informatics , p. 1 - 7 . https://doi.org/10.1109/ICOCI.2006.5276552 https://doi.org/10.1109/ICOCI.2006.5276552

Meng D , Zheng YL , 2022 . Circuit partitioning for PCB netlist based on net attributes . Int Conf on Machine Learning and Cybernetics , p. 31 - 36 . https://doi.org/10.1109/ICMLC56445.2022.9941328 https://doi.org/10.1109/ICMLC56445.2022.9941328

Mnih V , Kavukcuoglu K , Silver D , et al. , 2013 . Playing Atari with deep reinforcement learning . https://doi.org/10.48550/arXiv.1312.5602 https://doi.org/10.48550/arXiv.1312.5602

Ou HC , Chien HCC , Chang YW , 2014 . Nonuniform multilevel analog routing with matching constraints . IEEE Trans Computer-Aided Des Integr Circ Syst , 33 ( 12 ): 1942 - 1954 . https://doi.org/10.1109/TCAD.2014.2363394 https://doi.org/10.1109/TCAD.2014.2363394

Rematska G , Bourbakis NG , 2016 . A survey on reverse engineering of technical diagrams . 7 th Int Conf on Information , Intelligence, Systems & Applications , p. 1 - 8 . https://doi.org/10.1109/IISA.2016.7785372 https://doi.org/10.1109/IISA.2016.7785372

Roy R , Raiman J , Kant N , et al. , 2021 . PrefixRL: optimization of parallel prefix circuits using deep reinforcement learning . 58 th ACM/IEEE Design Automation Conf , p. 853 - 858 . https://doi.org/10.1109/DAC18074.2021.9586094 https://doi.org/10.1109/DAC18074.2021.9586094

Sechen C , 1988 . VLSI Placement and Global Routing Using Simulated Annealing . Springer , New York, USA , p. 181 - 243 . https://doi.org/10.1007/978-1-4613-1697-8 https://doi.org/10.1007/978-1-4613-1697-8

Sergey G , Daniil Z , Rustam C , 2019 . Simulated annealing based placement optimization for reconfigurable systems-on-chip . IEEE Conf of Russian Young Researchers in Electrical and Electronic Engineering , p. 1597 - 1600 . https://doi.org/10.1109/EIConRus.2019.8657251 https://doi.org/10.1109/EIConRus.2019.8657251

Sharma A , Dyrkolbotn GO , Overlier L , et al. , 2022 . A state-of-the-art reverse engineering approach for combating hardware security vulnerabilities at the system and PCB level in IoT devices . IEEE Physical Assurance and Inspection of Electronics , p. 1 - 7 . https://doi.org/10.1109/PAINE56030.2022.10014884 https://doi.org/10.1109/PAINE56030.2022.10014884

Shi YQ , Xue K , Lei S , et al. , 2023 . Macro placement by wire-mask-guided black-box optimization . Proc 37 th Int Conf on Neural Information Processing Systems , Article 299 .

Steinbrunn M , Moerkotte G , Kemper A , 1997 . Heuristic and randomized optimization for the join ordering problem . VLDB J , 6 ( 3 ): 191 - 208 . https://doi.org/10.1007/s007780050040 https://doi.org/10.1007/s007780050040

Stok L , Koster GP , 1989 . From network to artwork . Proc 26 th ACM/IEEE Design Automation Conf , p. 686 - 689 . https://doi.org/10.1145/74382.74504 https://doi.org/10.1145/74382.74504

Swinkels GM , Hafer L , 1990 . Schematic generation with an expert system . IEEE Trans Computer-Aided Des Integr Circ Syst , 9 ( 12 ): 1289 - 1306 . https://doi.org/10.1109/43.62774 https://doi.org/10.1109/43.62774

Tehranipoor M , Koushanfar F , 2010 . A survey of hardware Trojan taxonomy and detection . IEEE Des Test Comput , 27 ( 1 ): 10 - 25 . https://doi.org/10.1109/MDT.2010.7 https://doi.org/10.1109/MDT.2010.7

Vashisht D , Rampal H , Liao HG , et al. , 2020 . Placement in integrated circuits using cyclic reinforcement learning and simulated annealing . https://doi.org/10.48550/arXiv.2011.07577 https://doi.org/10.48550/arXiv.2011.07577

Wang HR , Wang K , Yang JC , et al. , 2020 . GCN-RL circuit designer: transferable transistor sizing with graph neural networks and reinforcement learning . 57 th ACM/IEEE Design Automation Conf , p. 1 - 6 . https://doi.org/10.1109/DAC18072.2020.9218757 https://doi.org/10.1109/DAC18072.2020.9218757

Wu CY , Graeb H , Hu J , 2015 . A pre-search assisted ILP approach to analog integrated circuit routing . 33 rd IEEE Int Conf on Computer Design , p. 244 - 250 . https://doi.org/10.1109/ICCD.2015.7357110 https://doi.org/10.1109/ICCD.2015.7357110

Wu YP , 2009 . Novel method of analog circuit schematic synthesis . IEEE 8 th Int Conf on ASIC , p. 1209 - 1212 . https://doi.org/10.1109/ASICON.2009.5351191 https://doi.org/10.1109/ASICON.2009.5351191

Yang J , Qiao K , Shi SH , et al. , 2024 . AEM-PCB reverser: circuit schematic generation in PCB reverse engineering using reinforcement learning based on aesthetic evaluation metric . IEEE Trans Computer-Aided Des Integr Circ Syst , 43 ( 5 ): 1608 - 1612 . https://doi.org/10.1109/TCAD.2023.3340869 https://doi.org/10.1109/TCAD.2023.3340869

Zhong RZ , Du XB , Kai SX , et al. , 2024a . FlexPlanner: flexible 3D floorplanning via deep reinforcement learning in hybrid action space with multi-modality representation . Proc 38 th Int Conf on Neural Information Processing Systems , p. 49252 - 49278 .

Zhong RZ , Ye JJ , Tang ZT , et al. , 2024b . PreRoutGNN for timing prediction with order preserving partition: global circuit pre-training, local delay learning and attentional cell modeling . Proc 38 th AAAI Conf on Artificial Intelligence , p. 17087 - 17095 . https://doi.org/10.1609/aaai.v38i15.29653 https://doi.org/10.1609/aaai.v38i15.29653

浏览量

Downloads

CSCD

文章被引用时，请邮件提醒。

Submit

工具集

关联资源

暂无数据