Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer

Di LI; Yin-tang YANG; Jiang-an WANG; Bing LI; Qiang LONG; Jary WEI; Nai-di WANG; Lei WANG; Qian-kun LIU; Da-long ZHANG

doi:10.1631/jzus.C0910381

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Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer

微电子 | Updated：2022-08-31

- Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
- Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
- 信息与电子工程前沿（英文） 2010年11卷第6期页码：444-449
- Affiliations：
  
  1.School of Microelectronics, Xidian University, Xi’an 710071, China
  2.Huaxun Microelectronics Corporation, Xi’an 710075, China
- Author bio：
  
  E-mail:lidi2004@126.com
- Funds：
- DOI：10.1631/jzus.C0910381
  中图分类号：
- 收稿：2009-06-28，
  
  修回：2010-05-04，
  
  录用：2009-12-22，
  
  纸质出版：2010-06
- Accepted：
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Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer[J]. 信息与电子工程前沿（英文）, 2010,11(6):444-449.

Di LI, Yin-tang YANG, Jiang-an WANG, et al. Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer[J]. Frontiers of Information Technology & Electronic Engineering, 2010, 11(6): 444-449.
Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer[J]. 信息与电子工程前沿（英文）, 2010,11(6):444-449. DOI： 10.1631/jzus.C0910381.

Di LI, Yin-tang YANG, Jiang-an WANG, et al. Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer[J]. Frontiers of Information Technology & Electronic Engineering, 2010, 11(6): 444-449. DOI： 10.1631/jzus.C0910381.

摘要

Abstract

A 19 mW highly integrated GPS receiver with a ΣΔ fractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work

to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure<2 dB

channel gain=108 dB (LNA1 included)

image rejection>36 dB

and −108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of −130 dBm. The chip operates over a temperature range of [−40

120] °C and ±5% tolerance over the CMOS technology process.

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