This paper presents an approach for analyzing the key parts of a general digital radio frequency (RF) charge sampling mixer based on discrete-time charge values. The cascade sampling and filtering stages are analyzed and expressed in theoretical formulae. The effects of a pseudo-differential structure and CMOS switch-on resistances on the transfer function are addressed in detail. The DC-gain is restrained by using the pseudo-differential structure. The transfer gain is reduced because of the charge-sharing time constant when taking CMOS switch-on resistances into account. The unfolded transfer gains of a typical digital RF charge sampling mixer are analyzed in different cases using this approach. A circuit-level model of the typical mixer is then constructed and simulated in Cadence SpectreRF to verify the results. This work informs the design of charge-sampling

infinite impulse response (IIR) filtering

and finite impulse response (FIR) filtering circuits. The discrete-time approach can also be applied to other multi-rate receiver systems based on charge sampling techniques.