To facilitate the application of support vector machines (SVMs) in embedded systems

we propose and test a parallel and scalable digital architecture based on the sequential minimal optimization (SMO) algorithm for training SVMs. By taking advantage of the mature and popular SMO algorithm

the numerical instability issues that may exist in traditional numerical algorithms are avoided. The error cache updating task

which dominates the computation time of the algorithm

is mapped into multiple processing units working in parallel. Experiment results show that using the proposed architecture

SVM training problems can be solved effectively with inexpensive fixed-point arithmetic and good scalability can be achieved. This architecture overcomes the drawbacks of the previously proposed SVM hardware that lacks the necessary flexibility for embedded applications

and thus is more suitable for embedded use

where scalability is an important concern.