An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays

Zhen-guo MA; Feng YU; Rui-feng GE; Ze-ke WANG

doi:10.1631/jzus.C1000258

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An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays

电子工程 | Updated：2022-08-31

- An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays
- An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays
- 信息与电子工程前沿（英文） 2011年12卷第4期页码：323-329
- Affiliations：
  
  Department of Instrument Engineering, Zhejiang University, Hangzhou 310027, China
- Author bio：
  
  E-mail:mzgzju@yahoo.com.cn
  ‡Corresponding Author
- Funds：
- DOI：10.1631/jzus.C1000258
  中图分类号：
- 收稿：2010-07-21，
  
  修回：2011-02-28，
  
  录用：2011-01-06，
  
  纸质出版：2011-04
- Accepted：
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An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. 信息与电子工程前沿（英文）, 2011,12(4):323-329.

Zhen-guo MA, Feng YU, Rui-feng GE, et al. An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(4): 323-329.
An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. 信息与电子工程前沿（英文）, 2011,12(4):323-329. DOI： 10.1631/jzus.C1000258.

Zhen-guo MA, Feng YU, Rui-feng GE, et al. An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(4): 323-329. DOI： 10.1631/jzus.C1000258.

摘要

Abstract

We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA). The FFT architecture exploits parallelism by having more pipelined units in the stages

and more parallel units within a stage. It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs)

and can be well matched to the placement of the resources on the FPGA. We adopt the decimation-in-frequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA. Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.

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相关机构

中国电子科技集团公司第58研究所

Institute of Cyber-Physical System Engineering, Northeastern University

Institute of Digital Technology and Instruments, Zhejiang University

Department of Electronic Science & Technology, Huazhong University of Science and Technology

State Key Lab of Modern Optical Instrumentation, Department of Optical Engineering, Zhejiang University

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