A power-aware code-compression design for RISC/VLIW architecture

Che-Wei LIN; Hong LIN; Jhih WANG

doi:10.1631/jzus.C1000321

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A power-aware code-compression design for RISC/VLIW architecture

计算机与自动化 | Updated：2022-08-31

- A power-aware code-compression design for RISC/VLIW architecture
- A power-aware code-compression design for RISC/VLIW architecture
- 信息与电子工程前沿（英文） 2011年12卷第8期页码：629-637
- Affiliations：
  
  Department of Electronic Engineering, National Taiwan University of Science and Technology, Taiwan 106, Taipei
- Author bio：
  
  ‡Corresponding Author
- Funds：
- DOI：10.1631/jzus.C1000321
  中图分类号：
- 收稿：2010-09-16，
  
  录用：2011-03-09，
  
  纸质出版：2011-08
- Accepted：
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A power-aware code-compression design for RISC/VLIW architecture[J]. 信息与电子工程前沿（英文）, 2011,12(8):629-637.

Che-Wei LIN, Hong LIN, Jhih WANG. A power-aware code-compression design for RISC/VLIW architecture[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(8): 629-637.
A power-aware code-compression design for RISC/VLIW architecture[J]. 信息与电子工程前沿（英文）, 2011,12(8):629-637. DOI： 10.1631/jzus.C1000321.

Che-Wei LIN, Hong LIN, Jhih WANG. A power-aware code-compression design for RISC/VLIW architecture[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(8): 629-637. DOI： 10.1631/jzus.C1000321.

摘要

Abstract

We studied the architecture of embedded computing systems from the viewpoint of power consumption in memory systems and used a selective-code-compression (SCC) approach to realize our design. Based on the LZW (Lempel-Ziv-Welch) compression algorithm

we propose a novel cost effective compression and decompression method. The goal of our study was to develop a new SCC approach with an extended decision policy based on the prediction of power consumption. Our decompression method had to be easily implemented in hardware and to collaborate with the embedded processor. The hardware implementation of our decompression engine uses the TSMC 0.18 μm-2p6m model and its cell-based libraries. To calculate power consumption more accurately

we used a static analysis method to estimate the power overhead of the decompression engine. We also used variable sized branch blocks and considered several features of very long instruction word (VLIW) processors for our compression

including the instruction level parallelism (ILP) technique and the scheduling of instructions. Our code-compression methods are not limited to VLIW machines

and can be applied to other kinds of reduced instruction set computer (RISC) architecture.

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