High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

Hossein AGHABABA; Behjat FOROUZANDEH; Ali AFZALI-KUSHA

doi:10.1631/jzus.C1100273

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High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

电子工程 | Updated：2022-12-09

- High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility
- High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility
- 信息与电子工程前沿（英文） 2012年13卷第6期页码：460-471
- Affiliations：
  
  Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran 14395, Iran
- Author bio：
  
  [ "Hossein AGHABABA, E-mail: h.aghababa@ece.ut.ac.ir" ]
- Funds：
- DOI：10.1631/jzus.C1100273
  中图分类号： TN4
- 收稿：2011-09-13，
  
  修回：2012-;4-;9，
  
  纸质出版：2012-06
- Accepted：
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High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility[J]. 信息与电子工程前沿（英文）, 2012,13(6):460-471.

Hossein AGHABABA, Behjat FOROUZANDEH, Ali AFZALI-KUSHA. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(6): 460-471.
High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility[J]. 信息与电子工程前沿（英文）, 2012,13(6):460-471. DOI： 10.1631/jzus.C1100273.

Hossein AGHABABA, Behjat FOROUZANDEH, Ali AFZALI-KUSHA. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(6): 460-471. DOI： 10.1631/jzus.C1100273.

摘要

Abstract

We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents

respectively

which are both affected by the variation of the threshold voltage. Additionally

the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations

which may be induced by any source. Using this model

in the plane of threshold voltage and mobility

we determine regions for different combinations of performance (speed) and leakage. Based on these regions

we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model

we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-

65-

and 90-nm technologies.

关键词

Keywords

references

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