
FOLLOWUS
1.Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
2.Department of Electrical and Electronic Engineering, Jiaxing University, Jiaxing 314001, China
3.College of Information Engineering, Zhejiang University of Technology, Hangzhou 310032, China
Lin-rong XIAO, E-mail: xiaolr@126.com
收稿:2011-10-07,
修回:2012-;4-11,
纸质出版:2012-05
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Design of dual-edge triggered flip-flops based on quantum-dot cellular automata[J]. 信息与电子工程前沿(英文), 2012,13(5):385-392.
Lin-rong XIAO, Xie-xiong CHEN, Shi-yan YING. Design of dual-edge triggered flip-flops based on quantum-dot cellular automata[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(5): 385-392.
Design of dual-edge triggered flip-flops based on quantum-dot cellular automata[J]. 信息与电子工程前沿(英文), 2012,13(5):385-392. DOI: 10.1631/jzus.C1100287.
Lin-rong XIAO, Xie-xiong CHEN, Shi-yan YING. Design of dual-edge triggered flip-flops based on quantum-dot cellular automata[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(5): 385-392. DOI: 10.1631/jzus.C1100287.
Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal–oxide–semiconductor (CMOS) due to QCA's inherent merits. Many interesting QCA-based logic circuits with smaller feature size
higher operating frequency
and lower power consumption than CMOS have been presented. However
QCA is limited in its sequential circuit design with high performance flip-flops. Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop
we propose two original QCA-based D and JK DET flip-flops
offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency. The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool. All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput. Furthermore
compared with a previous DET D flip-flop
the number of cells
covered area
and time delay of the proposed DET D flip-flop are reduced by 20.5%
23.5%
and 25%
respectively. By using a lower clock pulse frequency
the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.
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