A new via chain design method considering confidence level and estimation precision

Xiao-hua LUO; Li-sheng CHEN; Jiao-jiao ZHU; Xiao-lang YAN

doi:10.1631/jzus.C1200079

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A new via chain design method considering confidence level and estimation precision

电子工程 | Updated：2022-12-09

- A new via chain design method considering confidence level and estimation precision
- A new via chain design method considering confidence level and estimation precision
- 信息与电子工程前沿（英文） 2012年13卷第9期页码：702-710
- Affiliations：
  
  Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
- Author bio：
  
  [ "Xiao-hua LUO, E-mail: luoxh@vlsi.zju.edu.cn" ]
  [ "Li-sheng CHEN, E-mail: 05cls@zju.edu.cn" ]
- Funds：
  
  Project (No. 2009ZX02023-004-1) supported by the National Science and Technology Major Project, China
- DOI：10.1631/jzus.C1200079
  中图分类号： TN4
- 收稿：2012-03-26，
  
  修回：2012-;8-13，
  
  纸质出版：2012-09
- Accepted：
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A new via chain design method considering confidence level and estimation precision[J]. 信息与电子工程前沿（英文）, 2012,13(9):702-710.

Xiao-hua LUO, Li-sheng CHEN, Jiao-jiao ZHU, et al. A new via chain design method considering confidence level and estimation precision[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(9): 702-710.
A new via chain design method considering confidence level and estimation precision[J]. 信息与电子工程前沿（英文）, 2012,13(9):702-710. DOI： 10.1631/jzus.C1200079.

Xiao-hua LUO, Li-sheng CHEN, Jiao-jiao ZHU, et al. A new via chain design method considering confidence level and estimation precision[J]. Frontiers of Information Technology & Electronic Engineering, 2012, 13(9): 702-710. DOI： 10.1631/jzus.C1200079.

摘要

Abstract

For accurate prediction of via yield

via chains are usually fabricated on test chips to investigate issues about vias. To minimize the randomness of experiments and make the testing results more convincing

the confidence level and estimation precision of the via failure rate are investigated in this paper. Based on the Poisson yield model

the method of determining an adequate number of total vias is obtained using the law of large numbers and the de Moivre-Laplace theorem. Moreover

for a specific confidence level and estimation precision

the method of determining a suitable via chain length is proposed. For area minimization

an optimal combination of total vias and via chain length is further determined. Monte Carlo simulation results show that the method is in good accordance with theoretical analyses. Results of via failure rates measured on test chips also reveal that via chains designed using the proposed method has a better performance. In addition

the proposed methodology can be extended to investigate statistical significance for other failure modes.

关键词

Keywords

references

A. Cabrini , , , D. Cantarelli , , , P. Cappelletti , , , R. Casiraghi , , , A. Maurelli , , , M. Pasotti , , , P.L. Rolandi , , , G. Torelli . . A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies . . IEEE Trans. Semicond. Manuf. , , 2006 . . 19 ( ( 1 ): ): 57 - - 66 . . DOI: 10.1109/TSM.2005.863226 http://doi.org/10.1109/TSM.2005.863226 . .

G. de Cooman , , , E. Miranda . . Weak and strong laws of large numbers for coherent lower previsions . . J. Statist. Plann. Infer. , , 2008 . . 138 ( ( 8 ): ): 2409 - - 2432 . . DOI: 10.1016/j.jspi.2007.10.020 http://doi.org/10.1016/j.jspi.2007.10.020 . .

J. Gill , , , T. Sullivan , , , S. Yankee , , , H. Barth , , , A. von Glasow . . Investigation of Via-Dominated Multi-modal Electromigration Failure Distributions in Dual Damascene Cu Interconnects with a Discussion of the Statistical Implications . . Proc. 40th Annual Reliability Physics Symp. , , 2002 . . p.298 - - 304 . . DOI: 10.1109/relphy.2002.996652 http://doi.org/10.1109/relphy.2002.996652 . .

C. Hess , , , B.E. Stine , , , L.H. Weiland , , , T. Mitchell , , , M.P. Karnett , , , K. Gardner . . Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation . . IEEE Trans. Semicond. Manuf. , , 2003 . . 16 ( ( 2 ): ): 259 - - 265 . . DOI: 10.1109/TSM.2003.811939 http://doi.org/10.1109/TSM.2003.811939 . .

N. Konno . . Quantum random walks in one dimension . . Quant. Inf. Process. , , 2002 . . 1 ( ( 5 ): ): 345 - - 354 . . DOI: 10.1023/A:1023413713008 http://doi.org/10.1023/A:1023413713008 . .

Y.G. Li , , , S.H. Tan , , , W.R. Sun . . Test Structure Failed Node Localization and Analysis from Die Backside . . 15th Int. Symp. on the Physical and Failure Analysis of Integrated Circuits , , 2008 . . p.1 - - 3 . . DOI: 10.1109/IPFA.2008.4588165 http://doi.org/10.1109/IPFA.2008.4588165 . .

J. Liang , , , S. Chen , , , T. Yoshimura . . Redundant Via Insertion Based on Conflict Removal . . Proc. 10th IEEE Int. Conf. on Solid-State and Integrated Circuit Technology , , 2010 . . p. 794 - - 796 . . DOI: 10.1109/ICSICT.2010.5667425 http://doi.org/10.1109/ICSICT.2010.5667425 . .

Y. Matsubara , , , T. Watanabe . . 45nm Node Categorized Via Chain Resistance and Image by Optical Beam Induced Resistance Changes (OBIRCH) Method . . Proc. 44th Annual IEEE Int. Reliability Physics Symp. , , 2006 . . p.643 - - 644 . . DOI: 10.1109/RELPHY.2006.251303 http://doi.org/10.1109/RELPHY.2006.251303 . .

D.C. Montgomery , , , G.C. Runger . . Applied Statistics and Probability for Engineers , , 3rd Ed. John Wiley & Sons , , : : New York 2002 . . p.356 - - 359 . . . .

S. Morgan , , , I. de Munari , , , A. Scorzoni , , , F. Fantini , , , G. Magri , , , C. Zaccherini , , , C. Caprile . . Test Structures for Electromigration Evaluation in Submicron Technology . . Proc. IEEE Int. Conf. on Microelectronic Test Structures , , 1996 . . p.283 - - 287 . . DOI: 10.1109/ICMTS.1996.535661 http://doi.org/10.1109/ICMTS.1996.535661 . .

T. Nasuno , , , Y. Matsubara , , , A. Minami , , , N. Uchida , , , H. Kobayashi , , , H. Aoyama , , , H. Tsuda , , , K. Tsujita , , , W. Wakamiya , , , N. Kobayashi . . Test Structure for Fixing OPC of 200 nm Pitch Via Chain Using Inner and Outer Dummy Via Array . . Proc. Int. Conf. on Microelectronic Test Structures , , 2004 . . p.23 - - 28 . . DOI: 10.1109/ICMTS.2004.1309295 http://doi.org/10.1109/ICMTS.2004.1309295 . .

J.D. Plummer , , , M.D. Deal , , , P.B. Griffin . . Silocon VLSI Technology: Fundamentals, Practice, and Modeling . . Prentice Hall, Upper Saddle River, New Jersey , , 2000 . . p.157 . .

H.S. Rathore . . Via Resistance as a Technique to Control the Electromigration of Non-overlap Via Holes . . 20th Annual Reliability Physics Symp. , , 1982 . . p.77 - - 80 . . DOI: 10.1109/IRPS.1982.363025 http://doi.org/10.1109/IRPS.1982.363025 . .

D.Y. Shih , , , H. Yeh , , , C. Narayan , , , J. Lewis , , , W. Graham , , , S. Nunes , , , J. Paraszczak , , , R. McGouey , , , E. Galligan , , , J. Cataldo , , , 等 . . Factors Affecting the Interconnection Resistance and Yield in the Fabrication of Multilayer Polyimide/Metal Thin Film Structures . . Proc. 42nd Electronic Components and Technology Conf. , , 1992 . . p.1002 - - 1014 . . DOI: 10.1109/ECTC.1992.204328 http://doi.org/10.1109/ECTC.1992.204328 . .

C.H. Stapper . . Modeling of integrated circuit defect sensitivities . . IBM J. Res. Devel. , , 1983 . . 27 ( ( 6 ): ): 549 - - 557 . . DOI: 10.1147/rd.276.0549 http://doi.org/10.1147/rd.276.0549 . .

B.L. Welch . . The generalization of 'student's' problem when several different population variances are involved . . Biometrika , , 1947 . . 34 ( ( 1-2 ): ): 28 - - 35 . . DOI: 10.2307/2332510 http://doi.org/10.2307/2332510 . .

J.J. Zhu , , , X.H. Luo , , , L.S. Chen , , , Y. Ye , , , X.L. Yan . . Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process . . J. Zhejiang Univ.-Sci. C (Comput. & Electron.) , , 2012 . . 13 ( ( 5 ): ): 376 - - 384 . . DOI: 10.1631/jzus.C1100242 http://doi.org/10.1631/jzus.C1100242 . .

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