SAPER-AI加速器：一种基于脉动阵列的低能耗可重构人工智能加速器

Fahad Bin MUSLIM; Kashif INAYAT; Muhammad Zain SIDDIQI; Safiullah KHAN; Tayyeb MAHMOOD; Ihtesham ul ISLAM

doi:10.1631/FITEE.2400867

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SAPER-AI加速器：一种基于脉动阵列的低能耗可重构人工智能加速器

常规文章 | Updated：2025-11-05

- SAPER-AI加速器：一种基于脉动阵列的低能耗可重构人工智能加速器
- SAPER-AI accelerator: a systolic array-based power-efficient reconfigurable AI accelerator
- 信息与电子工程前沿（英文） 2025年26卷第9期页码：1624-1636
- Affiliations：
  
  1.Faculty of Computer Science and Engineering, GIK Institute, Topi 23460, Pakistan
  2.Barcelona Supercomputing Center, Barcelona 1-3 08034, Spain
  3.Department of Electronics Engineering, Incheon National University, Incheon 22006, Republic of Korea
  4.Department of Computing and Mathematics, Manchester Metropolitan University, Manchester M15 6BX, UK
  5.Nextwave Inc., Daejeon 34134, Republic of Korea
  6.Department of Computer Software Engineering, National University of Sciences and Technology, Islamabad H-12, Pakistan
- Author bio：
  
  ‡ Corresponding author
- Funds：
- DOI：10.1631/FITEE.2400867
  中图分类号： TP39
- 收稿：2024-09-21，
  
  修回：2025-01-24，
  
  网络出版：2025-09-16，
  
  纸质出版：2025-09
- Accepted：
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Fahad Bin MUSLIM, Kashif INAYAT, Muhammad Zain SIDDIQI, 等. SAPER-AI加速器：一种基于脉动阵列的低能耗可重构人工智能加速器[J]. 信息与电子工程前沿（英文）, 2025,26(9):1624-1636.

Fahad Bin MUSLIM, Kashif INAYAT, Muhammad Zain SIDDIQI, et al. SAPER-AI accelerator: a systolic array-based power-efficient reconfigurable AI accelerator[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1624-1636.
Fahad Bin MUSLIM, Kashif INAYAT, Muhammad Zain SIDDIQI, 等. SAPER-AI加速器：一种基于脉动阵列的低能耗可重构人工智能加速器[J]. 信息与电子工程前沿（英文）, 2025,26(9):1624-1636. DOI： 10.1631/FITEE.2400867.

Fahad Bin MUSLIM, Kashif INAYAT, Muhammad Zain SIDDIQI, et al. SAPER-AI accelerator: a systolic array-based power-efficient reconfigurable AI accelerator[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1624-1636. DOI： 10.1631/FITEE.2400867.

摘要

深度学习加速器对于满足现代神经网络日益增长的计算需求至关重要。基于脉动阵列的加速器由二维网格状的处理元件组成，这些处理元件协同工作以加速矩阵乘法运算。此类加速器的能效至关重要，尤其是在边缘人工智能场景下。本文提出的SAPER-AI加速器是一种脉动阵列加速器，采用统一功耗格式来定义其功耗意图，几乎无需优化其微架构。该加速器以粗粒度方式关闭处理元件的行和列，从而使脉动阵列微架构能适应现代深度学习工作负载不断变化的计算需求。分析表明，在最佳情况下，32×32和64×64脉动阵列设计的能效分别提升10%至25%。此外，更大规模的脉动阵列的功率延迟积改善约6%。进一步，基于MobileNet和ResNet50模型的性能比较表明，脉动阵列在处理ResNet50工作负载时通常表现更佳。这是因为ResNet50所呈现的更为规整的卷积计算更受脉动阵列青睐，且随着脉动阵列规模增大，这一性能差距会进一步扩大。

Abstract

Deep learning (DL) accelerators are critical for handling the growing computational demands of modern neural networks. Systolic array (SA)-based accelerators consist of a 2D mesh of processing elements (PEs) working cooperatively to accelerate matrix multiplication. The power efficiency of such accelerators is of primary importance

especially considering the edge AI regime. This work presents the SAPER-AI accelerator

an SA accelerator with power intent specified via a unified power format representation in a simplified manner with negligible microarchitectural optimization effort. Our proposed accelerator switches off rows and columns of PEs in a coarse-grained manner

thus leading to SA microarchitecture complying with the varying computational requirements of modern DL workloads. Our analysis demonstrates enhanced power efficiency ranging between 10% and 25% for the best case 32×32 and 64×64 SA designs

respectively. Additionally

the power delay product (PDP) exhibits a progressive improvement of around 6% for larger SA sizes. Moreover

a performance comparison between the MobileNet and ResNet50 models indicates generally better SA performance for the ResNet50 workload. This is due to the more regular convolutions portrayed by ResNet50 that are more favored by SAs

with the performance gap widening as the SA size increases.

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references

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