Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis

Zejia LYU; Jizhong SHEN; Xi CHEN

doi:10.1631/FITEE.2400677

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Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis

Regular Papers | Updated：2025-11-05

- Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis
- 面向集成电路功耗分析的伪数据集生成算法及评估
- Frontiers of Information Technology & Electronic Engineering Vol. 26, Issue 9, Pages: 1596-1608(2025)
- Affiliations：
  
  1.College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
  2.Shanghai Hexin Industrial Software Co., Ltd., Shanghai 201210, China
- Author bio：
  
  ‡ Corresponding author
- Funds：
- DOI：10.1631/FITEE.2400677
  CLC： TP391.7
- Received：02 August 2024，
  
  Revised：2025-03-07，
  
  Published Online：12 September 2025，
  
  Published：2025-09
- Accepted：
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Zejia LYU, Jizhong SHEN, Xi CHEN. Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1596-1608.
DOI：

Zejia LYU, Jizhong SHEN, Xi CHEN. Algorithm and evaluation of generating pseudo-datasets for integrated circuit power analysis[J]. Frontiers of Information Technology & Electronic Engineering, 2025, 26(9): 1596-1608. DOI： 10.1631/FITEE.2400677.

摘要

平均功耗分析在大规模数字集成电路设计中至关重要。随着以数据驱动为基础的机器学习方法在电子设计自动化（EDA）领域的应用，对海量数据集的需求日益增长。为满足这一需求，本文提出一种基于图拓扑结构的全新伪电路生成算法。该算法通过将随机生成的有向无环图转换为门级Verilog伪组合电路网表，高效生成海量功耗分析样本。随后引入寄存器单元，将伪组合网表转化为伪时序电路网表。通过超参数调控电路拓扑结构，并在综合过程中施加适当的时序约束，最终生成伪电路数据集。采用主流功耗分析软件评估该方法，对生成的电路进行布局前平均功耗测试，将其性能与基准数据集对比，并通过电路拓扑复杂度分析与静态时序分析验证结果。实验结果验证了数据集的有效性，展现了算法的高效运行和鲁棒性，彰显其研究价值。

Abstract

Average power analysis plays a crucial role in the design of large-scale digital integrated circuits (ICs). The integration of data-driven machine learning (ML) methods into the electronic design automation (EDA) fields has increased the demand for extensive datasets. To address this need

we propose a novel pseudo-circuit generation algorithm rooted in graph topology. This algorithm efficiently produces a multitude of power analysis examples by converting randomly generated directed acyclic graphs (DAGs) into gate-level Verilog pseudo-combinational circuit netlists. The subsequent introduction of register units transforms pseudo-combinational netlists into pseudo-sequential circuit netlists. Hyperparameters facilitate the control of circuit topology

while appropriate sequential constraints are applied during synthesis to yield a pseudo-circuit dataset. We evaluate our approach using the mainstream power analysis software

conducting pre-layout average power tests on the generated circuits

comparing their performance against benchmark datasets

and verifying the results through circuit topology complexity analysis and static timing analysis (STA). The results confirm the effectiveness of the dataset

and demonstrate the operational efficiency and robustness of the algorithm

underscoring its research value.

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references

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